From 7ab3fff68ff3f76f2f0ce5082850b71472c2dca5 Mon Sep 17 00:00:00 2001 From: Mike Blumenkrantz Date: Fri, 16 Jan 2026 14:48:14 -0500 Subject: [PATCH] zink: move the ntv sparse checks into ntv no functional changes Part-of: --- .../drivers/zink/nir_to_spirv/nir_to_spirv.c | 34 +++++++++++++------ src/gallium/drivers/zink/zink_compiler.c | 7 ---- 2 files changed, 24 insertions(+), 17 deletions(-) diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c index 71d380e4e34..0f5c584f3cb 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c +++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c @@ -42,6 +42,7 @@ struct ntv_context { bool have_spirv16; bool explicit_lod; //whether to set lod=0 for texture() + bool have_sparse; struct spirv_builder builder; nir_shader *nir; @@ -3567,6 +3568,22 @@ emit_launch_mesh_workgroups(struct ntv_context *ctx, nir_intrinsic_instr *intr) ctx->block_started = false; } +static void +init_sparse_resident(struct ntv_context *ctx) +{ + if (ctx->have_sparse) + return; + + spirv_builder_emit_cap(&ctx->builder, SpvCapabilitySparseResidency); + /* this could be huge, so only alloc if needed since it's extremely unlikely to + * ever be used by anything except cts + */ + ctx->resident_defs = rzalloc_array_size(ctx->mem_ctx, + sizeof(SpvId), + nir_shader_get_entrypoint(ctx->nir)->ssa_alloc); + ctx->have_sparse = true; +} + static void emit_intrinsic(struct ntv_context *ctx, nir_intrinsic_instr *intr) { @@ -3731,6 +3748,8 @@ emit_intrinsic(struct ntv_context *ctx, nir_intrinsic_instr *intr) break; case nir_intrinsic_image_deref_sparse_load: + init_sparse_resident(ctx); + FALLTHROUGH; case nir_intrinsic_image_deref_load: emit_image_deref_load(ctx, intr); break; @@ -3827,6 +3846,7 @@ emit_intrinsic(struct ntv_context *ctx, nir_intrinsic_instr *intr) break; case nir_intrinsic_is_sparse_resident_zink: + init_sparse_resident(ctx); emit_is_sparse_texels_resident(ctx, intr); break; @@ -4210,6 +4230,9 @@ emit_tex(struct ntv_context *ctx, nir_tex_instr *tex) tex->op == nir_texop_texture_samples || tex->op == nir_texop_query_levels); + if (tex->is_sparse) + init_sparse_resident(ctx); + struct spriv_tex_src tex_src = {0}; unsigned coord_components = 0; nir_variable *bindless_var = NULL; @@ -5241,16 +5264,7 @@ nir_to_spirv(struct nir_shader *s, const struct zink_shader_info *sinfo) sizeof(nir_alu_type), entry->ssa_alloc); if (!ctx.defs || !ctx.def_types) goto fail; - if (sinfo->have_sparse) { - spirv_builder_emit_cap(&ctx.builder, SpvCapabilitySparseResidency); - /* this could be huge, so only alloc if needed since it's extremely unlikely to - * ever be used by anything except cts - */ - ctx.resident_defs = rzalloc_array_size(ctx.mem_ctx, - sizeof(SpvId), entry->ssa_alloc); - if (!ctx.resident_defs) - goto fail; - } + ctx.num_defs = entry->ssa_alloc; SpvId *block_ids = ralloc_array_size(ctx.mem_ctx, diff --git a/src/gallium/drivers/zink/zink_compiler.c b/src/gallium/drivers/zink/zink_compiler.c index 95cf3d1a688..4648939238d 100644 --- a/src/gallium/drivers/zink/zink_compiler.c +++ b/src/gallium/drivers/zink/zink_compiler.c @@ -4659,10 +4659,6 @@ scan_nir(struct zink_screen *screen, nir_shader *shader, struct zink_shader *zs) nir_foreach_function_impl(impl, shader) { nir_foreach_block_safe(block, impl) { nir_foreach_instr_safe(instr, block) { - if (instr->type == nir_instr_type_tex) { - nir_tex_instr *tex = nir_instr_as_tex(instr); - zs->sinfo.have_sparse |= tex->is_sparse; - } if (instr->type != nir_instr_type_intrinsic) continue; nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr); @@ -4684,9 +4680,6 @@ scan_nir(struct zink_screen *screen, nir_shader *shader, struct zink_shader *zs) BITSET_SET_COUNT(shader->info.images_used, var->data.binding, MAX2(size, 1)); } - if (intr->intrinsic == nir_intrinsic_is_sparse_texels_resident || - intr->intrinsic == nir_intrinsic_image_deref_sparse_load) - zs->sinfo.have_sparse = true; bool is_load = false; bool is_input = false;