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i965: Enable the AMD_performance_monitor extension on Gen5+.

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Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke 2013-11-13 15:42:57 -08:00
parent 2af1aedeca
commit 7a70f033b5
1 changed files with 61 additions and 0 deletions
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61
src/mesa/drivers/dri/i965/intel_extensions.c
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@ -89,6 +89,64 @@ can_do_pipelined_register_writes(struct brw_context *brw)
return success;
}
static bool
can_write_oacontrol(struct brw_context *brw)
{
if (brw->gen < 6 || brw->gen >= 8)
return false;
/* Set "Select Context ID" to a particular address (which is likely not a
* context), but leave all counting disabled. This should be harmless.
*/
const int expected_value = 0x31337000;
const int offset = 110;
uint32_t *data;
/* Set a value in a BO to a known quantity. The workaround BO already
* exists and doesn't contain anything important, so we may as well use it.
*/
drm_intel_bo_map(brw->batch.workaround_bo, true);
data = brw->batch.workaround_bo->virtual;
data[offset] = 0xffffffff;
drm_intel_bo_unmap(brw->batch.workaround_bo);
/* Write OACONTROL. */
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(OACONTROL);
OUT_BATCH(expected_value);
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(brw);
/* Save the register's value back to the buffer. */
BEGIN_BATCH(3);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(OACONTROL);
OUT_RELOC(brw->batch.workaround_bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
offset * sizeof(uint32_t));
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(brw);
/* Set OACONTROL back to zero (everything off). */
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(OACONTROL);
OUT_BATCH(0);
ADVANCE_BATCH();
intel_batchbuffer_flush(brw);
/* Check whether the value got written. */
drm_intel_bo_map(brw->batch.workaround_bo, false);
bool success = data[offset] == expected_value;
drm_intel_bo_unmap(brw->batch.workaround_bo);
return success;
}
/**
* Initializes potential list of extensions if ctx == NULL, or actually enables
* extensions for a context.
@ -234,6 +292,9 @@ intelInitExtensions(struct gl_context *ctx)
}
}
if (brw->gen == 5 || can_write_oacontrol(brw))
ctx->Extensions.AMD_performance_monitor = true;
if (ctx->API == API_OPENGL_CORE)
ctx->Extensions.ARB_base_instance = true;
if (ctx->API != API_OPENGL_CORE)