From 7a3de9e8775b908fcf593bfdfc32410ebdc2fb55 Mon Sep 17 00:00:00 2001 From: Felix DeGrood Date: Thu, 8 Aug 2024 19:05:09 +0000 Subject: [PATCH] intel/brw: support for dumping shader line numbers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support for dumping shader asm containing instruction line numbers matching offsets within instruction state pool buffer. Offsets should match values collected from eu stall sampling. This is required for match eu stall data with individual shader instructions. Reviewed-by: José Roberto de Souza Part-of: --- src/intel/compiler/brw_disasm.c | 18 ++++++++++++++++-- src/intel/compiler/brw_disasm.h | 11 +++++++++-- src/intel/compiler/brw_disasm_info.cpp | 2 +- src/intel/compiler/brw_eu.c | 10 ++++++---- src/intel/compiler/intel_clc.c | 2 +- src/intel/decoder/intel_batch_decoder_brw.c | 2 +- src/intel/tools/intel_tools.c | 2 +- src/intel/vulkan/anv_pipeline.c | 3 ++- 8 files changed, 37 insertions(+), 13 deletions(-) diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index e0572b7c42c..dd23be6b701 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -2653,7 +2653,8 @@ brw_disassemble_find_end(const struct brw_isa_info *isa, void brw_disassemble_with_errors(const struct brw_isa_info *isa, - const void *assembly, int start, FILE *out) + const void *assembly, int start, + int64_t *lineno_offset, FILE *out) { int end = brw_disassemble_find_end(isa, assembly, start); @@ -2683,7 +2684,7 @@ brw_disassemble_with_errors(const struct brw_isa_info *isa, int end_offset = next->offset; brw_disassemble(isa, assembly, start_offset, end_offset, - root_label, out); + root_label, lineno_offset, out); if (group->error) { fputs(group->error, out); @@ -2693,3 +2694,16 @@ brw_disassemble_with_errors(const struct brw_isa_info *isa, ralloc_free(mem_ctx); ralloc_free(disasm_info); } + +void +brw_disassemble_with_lineno(const struct brw_isa_info *isa, uint32_t stage, + int dispatch_width, uint32_t src_hash, + const void *assembly, int start, + int64_t lineno_offset, FILE *out) +{ + fprintf(out, "\nDumping shader asm for %s", _mesa_shader_stage_to_abbrev(stage)); + if (dispatch_width > 0) + fprintf(out, " SIMD%i", dispatch_width); + fprintf(out, " (src_hash 0x%x):\n\n", src_hash); + brw_disassemble_with_errors(isa, assembly, start, &lineno_offset, out); +} diff --git a/src/intel/compiler/brw_disasm.h b/src/intel/compiler/brw_disasm.h index 5bc729e932d..54f54b33018 100644 --- a/src/intel/compiler/brw_disasm.h +++ b/src/intel/compiler/brw_disasm.h @@ -7,6 +7,7 @@ #include #include +#include #ifdef __cplusplus extern "C" { @@ -28,11 +29,17 @@ void brw_disassemble_with_labels(const struct brw_isa_info *isa, const void *assembly, int start, int end, FILE *out); void brw_disassemble(const struct brw_isa_info *isa, const void *assembly, int start, int end, - const struct brw_label *root_label, FILE *out); + const struct brw_label *root_label, + int64_t *lineno_offset, FILE *out); int brw_disassemble_find_end(const struct brw_isa_info *isa, const void *assembly, int start); void brw_disassemble_with_errors(const struct brw_isa_info *isa, - const void *assembly, int start, FILE *out); + const void *assembly, int start, + int64_t *lineno_offset, FILE *out); +void brw_disassemble_with_lineno(const struct brw_isa_info *isa, uint32_t stage, + int dispatch_width, uint32_t src_hash, + const void *assembly, int start, + int64_t lineno_offset, FILE *out); const char *brw_lsc_op_to_string(unsigned op); const char *brw_lsc_addr_surftype_to_string(unsigned t); diff --git a/src/intel/compiler/brw_disasm_info.cpp b/src/intel/compiler/brw_disasm_info.cpp index 5b856b2aa86..0b934d72a0a 100644 --- a/src/intel/compiler/brw_disasm_info.cpp +++ b/src/intel/compiler/brw_disasm_info.cpp @@ -70,7 +70,7 @@ dump_assembly(void *assembly, int start_offset, int end_offset, } brw_disassemble(isa, assembly, start_offset, end_offset, - root_label, stderr); + root_label, NULL, stderr); if (group->error) { fputs(group->error, stderr); diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c index 6fbd4efd3c3..dda92266135 100644 --- a/src/intel/compiler/brw_eu.c +++ b/src/intel/compiler/brw_eu.c @@ -31,6 +31,7 @@ #include #include +#include #include "brw_disasm.h" #include "brw_eu_defines.h" @@ -486,7 +487,7 @@ brw_disassemble_with_labels(const struct brw_isa_info *isa, const struct brw_label *root_label = brw_label_assembly(isa, assembly, start, end, mem_ctx); - brw_disassemble(isa, assembly, start, end, root_label, out); + brw_disassemble(isa, assembly, start, end, root_label, NULL, out); ralloc_free(mem_ctx); } @@ -494,7 +495,8 @@ brw_disassemble_with_labels(const struct brw_isa_info *isa, void brw_disassemble(const struct brw_isa_info *isa, const void *assembly, int start, int end, - const struct brw_label *root_label, FILE *out) + const struct brw_label *root_label, + int64_t *lineno_offset, FILE *out) { const struct intel_device_info *devinfo = isa->devinfo; @@ -512,8 +514,8 @@ brw_disassemble(const struct brw_isa_info *isa, } bool compacted = brw_eu_inst_cmpt_control(devinfo, insn); - if (0) - fprintf(out, "0x%08x: ", offset); + if (lineno_offset) + fprintf(out, "0x%08" PRIx64 ": ", *lineno_offset + offset); if (compacted) { brw_eu_compact_inst *compacted = (brw_eu_compact_inst *)insn; diff --git a/src/intel/compiler/intel_clc.c b/src/intel/compiler/intel_clc.c index 622b89439b0..4fd1ed6ce56 100644 --- a/src/intel/compiler/intel_clc.c +++ b/src/intel/compiler/intel_clc.c @@ -275,7 +275,7 @@ print_kernel(FILE *fp, const char *prefix, fprintf(fp, "#if 0 /* BEGIN KERNEL ASSEMBLY */\n"); fprintf(fp, "\n"); - brw_disassemble_with_errors(isa, kernel->code, 0, fp); + brw_disassemble_with_errors(isa, kernel->code, 0, NULL, fp); fprintf(fp, "\n"); fprintf(fp, "#endif /* END KERNEL ASSEMBLY */\n"); print_u32_data(fp, prefix, "code", kernel->code, diff --git a/src/intel/decoder/intel_batch_decoder_brw.c b/src/intel/decoder/intel_batch_decoder_brw.c index f8547116bd7..074c0297ec7 100644 --- a/src/intel/decoder/intel_batch_decoder_brw.c +++ b/src/intel/decoder/intel_batch_decoder_brw.c @@ -20,7 +20,7 @@ ctx_disassemble_program_brw(struct intel_batch_decode_ctx *ctx, return; fprintf(ctx->fp, "\nReferenced %s:\n", name); - brw_disassemble_with_errors(ctx->brw, bo.map, 0, ctx->fp); + brw_disassemble_with_errors(ctx->brw, bo.map, 0, NULL, ctx->fp); if (ctx->shader_binary) { int size = brw_disassemble_find_end(ctx->brw, bo.map, 0); diff --git a/src/intel/tools/intel_tools.c b/src/intel/tools/intel_tools.c index fcd2d2d6e6d..a697cba1fcb 100644 --- a/src/intel/tools/intel_tools.c +++ b/src/intel/tools/intel_tools.c @@ -28,7 +28,7 @@ intel_disassemble(const struct intel_device_info *devinfo, if (devinfo->ver >= 9) { struct brw_isa_info isa; brw_init_isa_info(&isa, devinfo); - brw_disassemble_with_errors(&isa, assembly, start, out); + brw_disassemble_with_errors(&isa, assembly, start, NULL, out); } else { #ifdef INTEL_USE_ELK struct elk_isa_info isa; diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 662ef0bfc56..f1d16b0583b 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -1682,7 +1682,8 @@ anv_pipeline_add_executable(struct anv_pipeline *pipeline, * do it for every binary. */ brw_disassemble_with_errors(&pipeline->device->physical->compiler->isa, - stage->code, code_offset, stream); + stage->code, code_offset, + &stage->bin->kernel.offset, stream); fclose(stream);