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r300: Remove unused RC_OPCODE_DPH

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Nothing generates it in the backend.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14211>
This commit is contained in:
Emma Anholt 2021-12-08 12:30:20 -08:00 • committed by Marge Bot
parent 9312bfb5fb
commit 7a22967de3
4 changed files with 1 additions and 28 deletions
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10
src/gallium/drivers/r300/compiler/radeon_opcodes.c
View file

@ -120,12 +120,6 @@ const struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
.NumSrcRegs = 2,
.HasDstReg = 1
},
{
.Opcode = RC_OPCODE_DPH,
.Name = "DPH",
.NumSrcRegs = 2,
.HasDstReg = 1
},
{
.Opcode = RC_OPCODE_DST,
.Name = "DST",
@ -529,10 +523,6 @@ void rc_compute_sources_for_writemask(
srcmasks[0] |= RC_MASK_XYZW;
srcmasks[1] |= RC_MASK_XYZW;
break;
case RC_OPCODE_DPH:
srcmasks[0] |= RC_MASK_XYZ;
srcmasks[1] |= RC_MASK_XYZW;
break;
case RC_OPCODE_TXB:
case RC_OPCODE_TXP:
case RC_OPCODE_TXL:

3
src/gallium/drivers/r300/compiler/radeon_opcodes.h
View file

@ -77,9 +77,6 @@ typedef enum {
/** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y + src0.z*src1.z + src0.w*src1.w */
RC_OPCODE_DP4,
/** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y + src0.z*src1.z + src1.w */
RC_OPCODE_DPH,
/** special instruction, see ARB_fragment_program */
RC_OPCODE_DST,

1
src/gallium/drivers/r300/compiler/radeon_pair_schedule.c
View file

@ -802,7 +802,6 @@ static int can_convert_opcode_to_alpha(unsigned int opcode)
case RC_OPCODE_DP2:
case RC_OPCODE_DP3:
case RC_OPCODE_DP4:
case RC_OPCODE_DPH:
return 0;
default:
return 1;

15
src/gallium/drivers/r300/compiler/radeon_program_alu.c
View file

@ -261,17 +261,6 @@ static void transform_DP2(struct radeon_compiler* c,
rc_remove_instruction(inst);
}
static void transform_DPH(struct radeon_compiler* c,
struct rc_instruction* inst)
{
struct rc_src_register src0 = inst->U.I.SrcReg[0];
src0.Negate &= ~RC_MASK_W;
src0.Swizzle &= ~(7 << (3 * 3));
src0.Swizzle |= RC_SWIZZLE_ONE << (3 * 3);
emit2(c, inst->Prev, RC_OPCODE_DP4, &inst->U.I, inst->U.I.DstReg, src0, inst->U.I.SrcReg[1]);
rc_remove_instruction(inst);
}
/**
* [1, src0.y*src1.y, src0.z, src1.w]
* So basically MUL with lotsa swizzling.
@ -591,7 +580,7 @@ static void transform_SUB(struct radeon_compiler* c,
* no userData necessary.
*
* Eliminates the following ALU instructions:
* CEIL, DPH, DST, FLR, LIT, LRP, POW, SEQ, SGE, SGT, SLE, SLT, SNE, SUB
* CEIL, DST, FLR, LIT, LRP, POW, SEQ, SGE, SGT, SLE, SLT, SNE, SUB
* using:
* MOV, ADD, MUL, MAD, FRC, DP3, LG2, EX2, CMP
*
@ -608,7 +597,6 @@ int radeonTransformALU(
switch(inst->U.I.Opcode) {
case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
case RC_OPCODE_DP2: transform_DP2(c, inst); return 1;
case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
case RC_OPCODE_DST: transform_DST(c, inst); return 1;
case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
case RC_OPCODE_LIT: transform_LIT(c, inst); return 1;
@ -839,7 +827,6 @@ int r300_transform_vertex_alu(
case RC_OPCODE_CMP: transform_r300_vertex_CMP(c, inst); return 1;
case RC_OPCODE_DP2: transform_r300_vertex_DP2(c, inst); return 1;
case RC_OPCODE_DP3: transform_r300_vertex_DP3(c, inst); return 1;
case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
case RC_OPCODE_LIT: transform_r300_vertex_fix_LIT(c, inst); return 1;
case RC_OPCODE_LRP: transform_LRP(c, inst); return 1;