diff --git a/src/intel/compiler/brw/tests/gen12/send.asm b/src/intel/compiler/brw/tests/gen12/send.asm
index d7c58c59109..f9620314d72 100644
--- a/src/intel/compiler/brw/tests/gen12/send.asm
+++ b/src/intel/compiler/brw/tests/gen12/send.asm
@@ -37,7 +37,5 @@ sendc(16)       nullUD          g119UD          nullUD          0x10031000
                             render MsgDesc: RT write SIMD16 LastRT Surface = 0  mlen 8 ex_mlen 0 rlen 0 { align1 1H @1 EOT };
 sendc(8)        nullUD          g125UD          g123UD          0x04031400                0x00000080
                             render MsgDesc: RT write SIMD8 LastRT Surface = 0  mlen 2 ex_mlen 2 rlen 0 { align1 1Q @1 EOT };
-sendc(16)       nullUD          g119UD          nullUD          0x10031000                0x00000000
-                            render MsgDesc: RT write SIMD16 LastRT Surface = 0  mlen 8 ex_mlen 0 rlen 0 { align1 1H @1 EOT };
 sendc(16)       nullUD          g123UD          g119UD          0x08031000                0x00000100
                             render MsgDesc: RT write SIMD16 LastRT Surface = 0  mlen 4 ex_mlen 4 rlen 0 { align1 1H @1 EOT };
diff --git a/src/intel/compiler/brw/tests/gen12/send.expected b/src/intel/compiler/brw/tests/gen12/send.expected
index 3ba1ebb53c2..225a2363a16 100644
--- a/src/intel/compiler/brw/tests/gen12/send.expected
+++ b/src/intel/compiler/brw/tests/gen12/send.expected
@@ -17,5 +17,4 @@
 31 45 00 80 00 00 0c 0f 0c 00 00 a0 00 00 78 02
 32 01 04 00 04 00 00 00 44 77 00 50 00 00 c4 00
 32 01 03 00 04 00 00 00 14 7d 00 58 14 7b c4 00
-32 01 04 00 04 00 00 00 44 77 00 50 00 00 c4 00
 32 01 04 00 04 00 00 00 24 7b 00 50 24 77 c4 00