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tu: fix rast state allocation size on a6xx gen4

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A few regs were added without changing the size of draw state.

Fixes: 4e05338d99 ("turnip: Rast updates for a6xx gen4")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13644>
This commit is contained in:
Danylo Piliaiev 2021-11-03 14:05:23 +02:00 • committed by Marge Bot
parent 675519f1d0
commit 79fcd63bd6
1 changed files with 3 additions and 1 deletions
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4
src/freedreno/vulkan/tu_pipeline.c
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@ -2779,7 +2779,9 @@ tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder,
}
struct tu_cs cs;
uint32_t cs_size = 9 + (builder->emit_msaa_state ? 11 : 0);
uint32_t cs_size = 9 +
(builder->device->physical_device->info->a6xx.has_shading_rate ? 8 : 0) +
(builder->emit_msaa_state ? 11 : 0);
pipeline->rast_state = tu_cs_draw_state(&pipeline->cs, &cs, cs_size);
tu_cs_emit_regs(&cs,