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freedreno/a6xx: Fix SP_CS_IBO address on a7xx

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This moved to accomidate the additional BINDLESS_BASE registers, and we
overlooked that when adding a7xx support.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35803>
This commit is contained in:
Rob Clark 2025-06-20 14:09:09 -07:00 • committed by Marge Bot
parent 029270f9c1
commit 79d2014d8b
2 changed files with 7 additions and 2 deletions
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6
src/freedreno/computerator/a6xx.cc
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@ -401,7 +401,11 @@ cs_ibo_emit(struct fd_ringbuffer *ring, struct fd_submit *submit,
CP_LOAD_STATE6_0_NUM_UNIT(kernel->num_bufs));
OUT_RB(ring, state);
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO, 2);
if (CHIP == A6XX) {
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO, 2);
} else {
OUT_PKT4(ring, REG_A7XX_SP_CS_IBO, 2);
}
OUT_RB(ring, state);
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);

3
src/freedreno/registers/adreno/a6xx.xml
View file

@ -5223,7 +5223,8 @@ to upconvert to 32b float internally?
<!--
IBO state for compute shader:
-->
<reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/>
<reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16" variants="A6XX"/>
<reg64 offset="0xa9f8" name="SP_CS_IBO" type="address" align="16" variants="A7XX"/>
<reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/>
<!-- Correlated with avgs/uvgs usage in FS -->