fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-30 20:50:09 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

amd/common: add ac_vgt_gs_mode() helper

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2017-12-15 15:37:19 +01:00
parent 55f8431c76
commit 79b34d0832
4 changed files with 42 additions and 55 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

27
src/amd/common/ac_shader_util.c
View file

@ -78,3 +78,30 @@ ac_get_cb_shader_mask(unsigned spi_shader_col_format)
}
return cb_shader_mask;
}
/**
* Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
* geometry shader.
*/
uint32_t
ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class)
{
unsigned cut_mode;
if (gs_max_vert_out <= 128) {
cut_mode = V_028A40_GS_CUT_128;
} else if (gs_max_vert_out <= 256) {
cut_mode = V_028A40_GS_CUT_256;
} else if (gs_max_vert_out <= 512) {
cut_mode = V_028A40_GS_CUT_512;
} else {
assert(gs_max_vert_out <= 1024);
cut_mode = V_028A40_GS_CUT_1024;
}
return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
S_028A40_CUT_MODE(cut_mode)|
S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
S_028A40_GS_WRITE_OPTIMIZE(1) |
S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
}

6
src/amd/common/ac_shader_util.h
View file

@ -25,6 +25,9 @@
#define AC_SHADER_UTIL_H
#include <stdbool.h>
#include <stdint.h>
#include "amd_family.h"
unsigned
ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
@ -33,4 +36,7 @@ ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
unsigned
ac_get_cb_shader_mask(unsigned spi_shader_col_format);
uint32_t
ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class);
#endif

32
src/amd/vulkan/radv_pipeline.c
View file

@ -1465,30 +1465,6 @@ static const struct radv_prim_vertex_count prim_size_table[] = {
[V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
};
static uint32_t si_vgt_gs_mode(struct radv_shader_variant *gs,
enum chip_class chip_class)
{
unsigned gs_max_vert_out = gs->info.gs.vertices_out;
unsigned cut_mode;
if (gs_max_vert_out <= 128) {
cut_mode = V_028A40_GS_CUT_128;
} else if (gs_max_vert_out <= 256) {
cut_mode = V_028A40_GS_CUT_256;
} else if (gs_max_vert_out <= 512) {
cut_mode = V_028A40_GS_CUT_512;
} else {
assert(gs_max_vert_out <= 1024);
cut_mode = V_028A40_GS_CUT_1024;
}
return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
S_028A40_CUT_MODE(cut_mode)|
S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
S_028A40_GS_WRITE_OPTIMIZE(1) |
S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
}
static struct ac_vs_output_info *get_vs_output_info(struct radv_pipeline *pipeline)
{
if (radv_pipeline_has_gs(pipeline))
@ -1507,8 +1483,12 @@ static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
pipeline->graphics.vgt_gs_mode = 0;
if (radv_pipeline_has_gs(pipeline)) {
pipeline->graphics.vgt_gs_mode = si_vgt_gs_mode(pipeline->shaders[MESA_SHADER_GEOMETRY],
pipeline->device->physical_device->rad_info.chip_class);
struct radv_shader_variant *gs =
pipeline->shaders[MESA_SHADER_GEOMETRY];
pipeline->graphics.vgt_gs_mode =
ac_vgt_gs_mode(gs->info.gs.vertices_out,
pipeline->device->physical_device->rad_info.chip_class);
} else if (outinfo->export_prim_id) {
pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
pipeline->graphics.vgt_primitiveid_en = true;

32
src/gallium/drivers/radeonsi/si_state_shaders.c
View file

@ -573,34 +573,6 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
}
/**
* Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
* geometry shader.
*/
static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
{
enum chip_class chip_class = sel->screen->info.chip_class;
unsigned gs_max_vert_out = sel->gs_max_out_vertices;
unsigned cut_mode;
if (gs_max_vert_out <= 128) {
cut_mode = V_028A40_GS_CUT_128;
} else if (gs_max_vert_out <= 256) {
cut_mode = V_028A40_GS_CUT_256;
} else if (gs_max_vert_out <= 512) {
cut_mode = V_028A40_GS_CUT_512;
} else {
assert(gs_max_vert_out <= 1024);
cut_mode = V_028A40_GS_CUT_1024;
}
return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
S_028A40_CUT_MODE(cut_mode)|
S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
S_028A40_GS_WRITE_OPTIMIZE(1) |
S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
}
struct gfx9_gs_info {
unsigned es_verts_per_subgroup;
unsigned gs_prims_per_subgroup;
@ -867,7 +839,9 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
} else {
si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
ac_vgt_gs_mode(gs->gs_max_out_vertices,
sscreen->info.chip_class));
si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
}