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radv: Select correct entries for binning.

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Overshot it by one every time.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 82664af6cf)
This commit is contained in:
Bas Nieuwenhuizen 2018-07-14 14:28:21 +02:00 • committed by Dylan Baker
parent 630eacdaa5
commit 79a247b233
1 changed files with 2 additions and 2 deletions
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4
src/amd/vulkan/radv_pipeline.c
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@ -2462,7 +2462,7 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
}
const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
while(color_entry->bpp <= color_bytes_per_pixel)
while(color_entry[1].bpp <= color_bytes_per_pixel)
++color_entry;
extent = color_entry->extent;
@ -2476,7 +2476,7 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr
unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
while(ds_entry->bpp <= ds_bytes_per_pixel)
while(ds_entry[1].bpp <= ds_bytes_per_pixel)
++ds_entry;
extent.width = MIN2(extent.width, ds_entry->extent.width);