fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-08 09:08:10 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

intel/isl: Update mocs for DG1

Browse source 
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
This commit is contained in:
Rafael Antognolli 2019-11-05 15:34:53 -08:00 • committed by Jordan Justen
parent 3daa866751
commit 793b409241
1 changed files with 14 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

19
src/intel/isl/isl.c
View file

@ -99,11 +99,20 @@ static void
isl_device_setup_mocs(struct isl_device *dev)
{
if (dev->info->gen >= 12) {
/* TODO: Set PTE to MOCS 61 when the kernel is ready */
/* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
dev->mocs.external = 3 << 1;
/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
dev->mocs.internal = 2 << 1;
if (dev->info->is_dg1) {
/* L3CC=WB */
dev->mocs.internal = 5 << 1;
/* Displayables on DG1 are free to cache in L3 since L3 is transient
* and flushed at bottom of each submission.
*/
dev->mocs.external = 5 << 1;
} else {
/* TODO: Set PTE to MOCS 61 when the kernel is ready */
/* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
dev->mocs.external = 3 << 1;
/* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
dev->mocs.internal = 2 << 1;
}
} else if (dev->info->gen >= 9) {
/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
dev->mocs.external = 1 << 1;