diff --git a/src/gallium/frontends/rusticl/core/memory.rs b/src/gallium/frontends/rusticl/core/memory.rs
index eaafa060a1e..d991028b72e 100644
--- a/src/gallium/frontends/rusticl/core/memory.rs
+++ b/src/gallium/frontends/rusticl/core/memory.rs
@@ -699,20 +699,6 @@ impl MemBase {
         Ok(self.tx_raw(q, ctx, offset, size, rw)?.with_ctx(ctx))
     }
 
-    fn tx_image_raw(
-        &self,
-        q: &Queue,
-        ctx: &PipeContext,
-        bx: &pipe_box,
-        rw: RWFlags,
-    ) -> CLResult<PipeTransfer> {
-        assert!(!self.is_buffer());
-
-        let r = self.get_res()?.get(&q.device).unwrap();
-        ctx.texture_map(r, bx, rw, ResourceMapType::Normal)
-            .ok_or(CL_OUT_OF_RESOURCES)
-    }
-
     fn tx_image_raw_async(
         &self,
         dev: &Device,
@@ -753,16 +739,6 @@ impl MemBase {
         }
     }
 
-    fn tx_image<'a>(
-        &self,
-        q: &Queue,
-        ctx: &'a PipeContext,
-        bx: &pipe_box,
-        rw: RWFlags,
-    ) -> CLResult<GuardedPipeTransfer<'a>> {
-        Ok(self.tx_image_raw(q, ctx, bx, rw)?.with_ctx(ctx))
-    }
-
     pub fn has_same_parent(&self, other: &Self) -> bool {
         ptr::eq(self.get_parent(), other.get_parent())
     }
@@ -1530,6 +1506,20 @@ impl Image {
         }
     }
 
+    fn tx_image<'a>(
+        &self,
+        q: &Queue,
+        ctx: &'a PipeContext,
+        bx: &pipe_box,
+        rw: RWFlags,
+    ) -> CLResult<GuardedPipeTransfer<'a>> {
+        let r = self.get_res_of_dev(q.device)?;
+        Ok(ctx
+            .texture_map(r, bx, rw, ResourceMapType::Normal)
+            .ok_or(CL_OUT_OF_RESOURCES)?
+            .with_ctx(ctx))
+    }
+
     // TODO: only sync on unmap when the memory is not mapped for writing
     pub fn unmap(&self, q: &Queue, ctx: &PipeContext, ptr: *mut c_void) -> CLResult<()> {
         let mut lock = self.maps.lock().unwrap();