mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-01-03 09:20:13 +01:00
Initial conditional execution support for loops and BRK instruction.
Also, instead of passing cond mask to each micro op, just apply it in the store_dest() function.
This commit is contained in:
Brian
parent
91550f0a17
commit
78f3cd1e08
2 changed files with 110 additions and 94 deletions
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@ -54,6 +54,12 @@
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FOR_EACH_CHANNEL( CHAN )\
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if (IS_CHANNEL_ENABLED2( INST, CHAN ))
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/** The execution mask depends on the conditional mask and the loop mask */
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#define UPDATE_EXEC_MASK(MACH) \
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MACH->ExecMask = MACH->CondMask & MACH->LoopMask
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#define CHAN_X 0
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#define CHAN_Y 1
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#define CHAN_Z 2
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@ -98,6 +104,8 @@ tgsi_exec_machine_init(
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}
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mach->CondMask = 0xf;
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mach->LoopMask = 0xf;
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mach->ExecMask = 0xf;
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}
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void
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@ -177,17 +185,12 @@ static void
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micro_add(
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union tgsi_exec_channel *dst,
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const union tgsi_exec_channel *src0,
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const union tgsi_exec_channel *src1,
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uint mask)
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const union tgsi_exec_channel *src1 )
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{
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if (mask & 0x1)
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dst->f[0] = src0->f[0] + src1->f[0];
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if (mask & 0x2)
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dst->f[1] = src0->f[1] + src1->f[1];
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if (mask & 0x4)
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dst->f[2] = src0->f[2] + src1->f[2];
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if (mask & 0x8)
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dst->f[3] = src0->f[3] + src1->f[3];
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dst->f[0] = src0->f[0] + src1->f[0];
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dst->f[1] = src0->f[1] + src1->f[1];
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dst->f[2] = src0->f[2] + src1->f[2];
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dst->f[3] = src0->f[3] + src1->f[3];
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}
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static void
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@ -313,7 +316,7 @@ micro_ieq(
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static void
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micro_exp2(
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union tgsi_exec_channel *dst,
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const union tgsi_exec_channel *src )
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const union tgsi_exec_channel *src)
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{
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dst->f[0] = (GLfloat) pow( 2.0, (GLdouble) src->f[0] );
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dst->f[1] = (GLfloat) pow( 2.0, (GLdouble) src->f[1] );
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@ -531,17 +534,12 @@ static void
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micro_mul(
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union tgsi_exec_channel *dst,
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const union tgsi_exec_channel *src0,
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const union tgsi_exec_channel *src1,
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uint condMask)
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const union tgsi_exec_channel *src1 )
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{
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if (condMask & 0x1)
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dst->f[0] = src0->f[0] * src1->f[0];
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if (condMask & 0x2)
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dst->f[1] = src0->f[1] * src1->f[1];
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if (condMask & 0x4)
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dst->f[2] = src0->f[2] * src1->f[2];
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if (condMask & 0x8)
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dst->f[3] = src0->f[3] * src1->f[3];
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dst->f[0] = src0->f[0] * src1->f[0];
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dst->f[1] = src0->f[1] * src1->f[1];
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dst->f[2] = src0->f[2] * src1->f[2];
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dst->f[3] = src0->f[3] * src1->f[3];
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}
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static void
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@ -732,17 +730,12 @@ static void
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micro_sub(
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union tgsi_exec_channel *dst,
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const union tgsi_exec_channel *src0,
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const union tgsi_exec_channel *src1,
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uint mask)
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const union tgsi_exec_channel *src1 )
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{
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if (mask & 0x1)
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dst->f[0] = src0->f[0] - src1->f[0];
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if (mask & 0x2)
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dst->f[1] = src0->f[1] - src1->f[1];
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if (mask & 0x4)
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dst->f[2] = src0->f[2] - src1->f[2];
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if (mask & 0x8)
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dst->f[3] = src0->f[3] - src1->f[3];
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dst->f[0] = src0->f[0] - src1->f[0];
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dst->f[1] = src0->f[1] - src1->f[1];
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dst->f[2] = src0->f[2] - src1->f[2];
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dst->f[3] = src0->f[3] - src1->f[3];
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}
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static void
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@ -957,8 +950,7 @@ store_dest(
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const union tgsi_exec_channel *chan,
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const struct tgsi_full_dst_register *reg,
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const struct tgsi_full_instruction *inst,
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GLuint chan_index,
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uint mask)
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GLuint chan_index )
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{
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union tgsi_exec_channel *dst;
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@ -989,13 +981,13 @@ store_dest(
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#if 0
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*dst = *chan;
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#else
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if (mask & 0x1)
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if (mach->ExecMask & 0x1)
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dst->i[0] = chan->i[0];
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if (mask & 0x2)
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if (mach->ExecMask & 0x2)
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dst->i[1] = chan->i[1];
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if (mask & 0x4)
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if (mach->ExecMask & 0x4)
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dst->i[2] = chan->i[2];
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if (mask & 0x8)
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if (mach->ExecMask & 0x8)
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dst->i[3] = chan->i[3];
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#endif
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break;
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@ -1018,10 +1010,8 @@ store_dest(
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fetch_source (mach, VAL, &inst->FullSrcRegisters[INDEX], CHAN)
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#define STORE(VAL,INDEX,CHAN)\
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store_dest (mach, VAL, &inst->FullDstRegisters[INDEX], inst, CHAN, ~0)
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store_dest (mach, VAL, &inst->FullDstRegisters[INDEX], inst, CHAN )
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#define STORE_MASKED(VAL,INDEX,CHAN,MASK) \
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store_dest (mach, VAL, &inst->FullDstRegisters[INDEX], inst, CHAN, MASK)
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static void
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exec_kil (struct tgsi_exec_machine *mach,
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@ -1242,7 +1232,7 @@ exec_instruction(
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/* TGSI_OPCODE_SWZ */
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FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
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FETCH( &r[0], 0, chan_index );
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STORE_MASKED( &r[0], 0, chan_index, mach->CondMask );
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STORE( &r[0], 0, chan_index );
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}
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break;
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@ -1309,7 +1299,7 @@ exec_instruction(
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FETCH(&r[0], 0, chan_index);
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FETCH(&r[1], 1, chan_index);
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[0], &r[0], &r[1] );
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STORE(&r[0], 0, chan_index);
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}
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@ -1319,7 +1309,7 @@ exec_instruction(
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FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
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FETCH( &r[0], 0, chan_index );
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FETCH( &r[1], 1, chan_index );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1] );
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STORE( &r[0], 0, chan_index );
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}
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break;
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@ -1328,17 +1318,17 @@ exec_instruction(
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/* TGSI_OPCODE_DOT3 */
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FETCH( &r[0], 0, CHAN_X );
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FETCH( &r[1], 1, CHAN_X );
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[0], &r[0], &r[1] );
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FETCH( &r[1], 0, CHAN_Y );
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FETCH( &r[2], 1, CHAN_Y );
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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FETCH( &r[1], 0, CHAN_Z );
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FETCH( &r[2], 1, CHAN_Z );
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
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STORE( &r[0], 0, chan_index );
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@ -1350,25 +1340,25 @@ exec_instruction(
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FETCH(&r[0], 0, CHAN_X);
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FETCH(&r[1], 1, CHAN_X);
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[0], &r[0], &r[1] );
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FETCH(&r[1], 0, CHAN_Y);
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FETCH(&r[2], 1, CHAN_Y);
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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FETCH(&r[1], 0, CHAN_Z);
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FETCH(&r[2], 1, CHAN_Z);
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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FETCH(&r[1], 0, CHAN_W);
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FETCH(&r[2], 1, CHAN_W);
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
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STORE( &r[0], 0, chan_index );
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@ -1383,7 +1373,7 @@ exec_instruction(
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if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
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FETCH( &r[0], 0, CHAN_Y );
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FETCH( &r[1], 1, CHAN_Y);
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[0], &r[0], &r[1] );
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STORE( &r[0], 0, CHAN_Y );
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}
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@ -1416,7 +1406,7 @@ exec_instruction(
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micro_lt( &r[0], &r[0], &r[1], &r[1], &r[0] );
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STORE(&r[0], 0, chan_index);
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STORE(&r[0], 0, chan_index );
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}
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break;
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@ -1445,9 +1435,9 @@ exec_instruction(
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FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
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FETCH( &r[0], 0, chan_index );
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FETCH( &r[1], 1, chan_index );
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[0], &r[0], &r[1] );
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FETCH( &r[1], 2, chan_index );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1] );
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STORE( &r[0], 0, chan_index );
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}
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break;
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@ -1457,7 +1447,7 @@ exec_instruction(
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FETCH(&r[0], 0, chan_index);
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FETCH(&r[1], 1, chan_index);
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micro_sub( &r[0], &r[0], &r[1], mach->CondMask );
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micro_sub( &r[0], &r[0], &r[1] );
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STORE(&r[0], 0, chan_index);
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}
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@ -1470,9 +1460,9 @@ exec_instruction(
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FETCH(&r[1], 1, chan_index);
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FETCH(&r[2], 2, chan_index);
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micro_sub( &r[1], &r[1], &r[2], mach->CondMask );
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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micro_add( &r[0], &r[0], &r[2], mach->CondMask );
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micro_sub( &r[1], &r[1], &r[2] );
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micro_mul( &r[0], &r[0], &r[1] );
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micro_add( &r[0], &r[0], &r[2] );
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STORE(&r[0], 0, chan_index);
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}
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@ -1566,13 +1556,13 @@ exec_instruction(
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FETCH(&r[0], 0, CHAN_Y);
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FETCH(&r[1], 1, CHAN_Z);
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micro_mul( &r[2], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[2], &r[0], &r[1] );
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FETCH(&r[3], 0, CHAN_Z);
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FETCH(&r[4], 1, CHAN_Y);
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micro_mul( &r[5], &r[3], &r[4], mach->CondMask );
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micro_sub( &r[2], &r[2], &r[5], mach->CondMask );
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micro_mul( &r[5], &r[3], &r[4] );
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micro_sub( &r[2], &r[2], &r[5] );
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if (IS_CHANNEL_ENABLED( *inst, CHAN_X )) {
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STORE( &r[2], 0, CHAN_X );
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@ -1580,20 +1570,20 @@ exec_instruction(
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FETCH(&r[2], 1, CHAN_X);
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micro_mul( &r[3], &r[3], &r[2], mach->CondMask );
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micro_mul( &r[3], &r[3], &r[2] );
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FETCH(&r[5], 0, CHAN_X);
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micro_mul( &r[1], &r[1], &r[5], mach->CondMask );
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micro_sub( &r[3], &r[3], &r[1], mach->CondMask );
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micro_mul( &r[1], &r[1], &r[5] );
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micro_sub( &r[3], &r[3], &r[1] );
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if (IS_CHANNEL_ENABLED( *inst, CHAN_Y )) {
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STORE( &r[3], 0, CHAN_Y );
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}
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micro_mul( &r[5], &r[5], &r[4], mach->CondMask );
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micro_mul( &r[0], &r[0], &r[2], mach->CondMask );
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micro_sub( &r[5], &r[5], &r[0], mach->CondMask );
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micro_mul( &r[5], &r[5], &r[4] );
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micro_mul( &r[0], &r[0], &r[2] );
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micro_sub( &r[5], &r[5], &r[0] );
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if (IS_CHANNEL_ENABLED( *inst, CHAN_Z )) {
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STORE( &r[5], 0, CHAN_Z );
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@ -1626,23 +1616,23 @@ exec_instruction(
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FETCH(&r[0], 0, CHAN_X);
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FETCH(&r[1], 1, CHAN_X);
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[0], &r[0], &r[1] );
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FETCH(&r[1], 0, CHAN_Y);
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FETCH(&r[2], 1, CHAN_Y);
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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FETCH(&r[1], 0, CHAN_Z);
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FETCH(&r[2], 1, CHAN_Z);
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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FETCH(&r[1], 1, CHAN_W);
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1] );
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FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
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STORE( &r[0], 0, chan_index );
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@ -1925,12 +1915,12 @@ exec_instruction(
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case TGSI_OPCODE_DP2:
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FETCH( &r[0], 0, CHAN_X );
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FETCH( &r[1], 1, CHAN_X );
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micro_mul( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[0], &r[0], &r[1] );
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FETCH( &r[1], 0, CHAN_Y );
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FETCH( &r[2], 1, CHAN_Y );
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micro_mul( &r[1], &r[1], &r[2], mach->CondMask );
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micro_add( &r[0], &r[0], &r[1], mach->CondMask );
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micro_mul( &r[1], &r[1], &r[2] );
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micro_add( &r[0], &r[0], &r[1] );
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FOR_EACH_ENABLED_CHANNEL( *inst, chan_index ) {
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STORE( &r[0], 0, chan_index );
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@ -1942,12 +1932,15 @@ exec_instruction(
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break;
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case TGSI_OPCODE_BRK:
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assert (0);
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/* turn off loop channels for each enabled exec channel */
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mach->LoopMask &= ~mach->ExecMask;
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UPDATE_EXEC_MASK(mach);
|
||||
break;
|
||||
|
||||
case TGSI_OPCODE_IF:
|
||||
/* push CondMask */
|
||||
mach->condStack[mach->CondStackTop++] = mach->CondMask;
|
||||
assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
|
||||
mach->CondStack[mach->CondStackTop++] = mach->CondMask;
|
||||
FETCH( &r[0], 0, CHAN_X );
|
||||
/* update CondMask */
|
||||
if( ! r[0].u[0] ) {
|
||||
|
|
@ -1962,10 +1955,13 @@ exec_instruction(
|
|||
if( ! r[0].u[3] ) {
|
||||
mach->CondMask &= ~0x8;
|
||||
}
|
||||
UPDATE_EXEC_MASK(mach);
|
||||
break;
|
||||
|
||||
case TGSI_OPCODE_LOOP:
|
||||
assert (0);
|
||||
/* push LoopMask */
|
||||
assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
|
||||
mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
|
||||
break;
|
||||
|
||||
case TGSI_OPCODE_REP:
|
||||
|
|
@ -1977,20 +1973,25 @@ exec_instruction(
|
|||
{
|
||||
uint prevMask;
|
||||
assert(mach->CondStackTop > 0);
|
||||
prevMask = mach->condStack[mach->CondStackTop - 1];
|
||||
prevMask = mach->CondStack[mach->CondStackTop - 1];
|
||||
mach->CondMask = ~mach->CondMask & prevMask;
|
||||
UPDATE_EXEC_MASK(mach);
|
||||
}
|
||||
break;
|
||||
|
||||
case TGSI_OPCODE_ENDIF:
|
||||
assert(mach->CondStackTop > 0);
|
||||
/* pop CondMask */
|
||||
mach->CondMask = mach->condStack[--mach->CondStackTop];
|
||||
assert(mach->CondStackTop > 0);
|
||||
mach->CondMask = mach->CondStack[--mach->CondStackTop];
|
||||
UPDATE_EXEC_MASK(mach);
|
||||
break;
|
||||
|
||||
case TGSI_OPCODE_ENDLOOP:
|
||||
assert (0);
|
||||
break;
|
||||
/* pop LoopMask */
|
||||
assert(mach->LoopStackTop > 0);
|
||||
mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
|
||||
UPDATE_EXEC_MASK(mach);
|
||||
break;
|
||||
|
||||
case TGSI_OPCODE_ENDREP:
|
||||
assert (0);
|
||||
|
|
@ -2109,7 +2110,9 @@ exec_instruction(
|
|||
break;
|
||||
|
||||
case TGSI_OPCODE_BGNLOOP2:
|
||||
assert( 0 );
|
||||
/* push LoopMask */
|
||||
assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
|
||||
mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
|
||||
break;
|
||||
|
||||
case TGSI_OPCODE_BGNSUB:
|
||||
|
|
@ -2117,7 +2120,10 @@ exec_instruction(
|
|||
break;
|
||||
|
||||
case TGSI_OPCODE_ENDLOOP2:
|
||||
assert( 0 );
|
||||
/* pop LoopMask */
|
||||
assert(mach->LoopStackTop > 0);
|
||||
mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
|
||||
UPDATE_EXEC_MASK(mach);
|
||||
break;
|
||||
|
||||
case TGSI_OPCODE_ENDSUB:
|
||||
|
|
|
|||
|
|
@ -98,8 +98,12 @@ struct tgsi_exec_labels
|
|||
#define TGSI_EXEC_NUM_ADDRS 1
|
||||
|
||||
#define TGSI_EXEC_MAX_COND_NESTING 10
|
||||
#define TGSI_EXEC_MAX_LOOP_NESTING 10
|
||||
|
||||
|
||||
/**
|
||||
* Run-time virtual machine state for executing TGSI shader.
|
||||
*/
|
||||
struct tgsi_exec_machine
|
||||
{
|
||||
/*
|
||||
|
|
@ -132,12 +136,18 @@ struct tgsi_exec_machine
|
|||
/* FRAGMENT processor only. */
|
||||
const struct tgsi_interp_coef *InterpCoefs;
|
||||
|
||||
/* Conditional execution mask */
|
||||
/* Conditional execution masks */
|
||||
uint CondMask;
|
||||
uint LoopMask;
|
||||
uint ExecMask; /**< = CondMask & LoopMask */
|
||||
|
||||
/* Condition mask stack (for nested conditionals) */
|
||||
uint condStack[TGSI_EXEC_MAX_COND_NESTING];
|
||||
/** Condition mask stack (for nested conditionals) */
|
||||
uint CondStack[TGSI_EXEC_MAX_COND_NESTING];
|
||||
int CondStackTop;
|
||||
|
||||
/** Loop mask stack (for nested loops) */
|
||||
uint LoopStack[TGSI_EXEC_MAX_LOOP_NESTING];
|
||||
int LoopStackTop;
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue