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ir3/opt_preamble: take alias.rt into account for rewrite cost

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FS outputs can use const registers in alias.rt without a mov so take
this into account when calculating the rewrite cost of instructions.

Totals:
MaxWaves: 2765084 -> 2765130 (+0.00%); split: +0.00%, -0.00%
Instrs: 56289002 -> 56285073 (-0.01%); split: -0.01%, +0.00%
CodeSize: 118071672 -> 118076808 (+0.00%); split: -0.00%, +0.01%
NOPs: 9491112 -> 9492474 (+0.01%); split: -0.00%, +0.02%
MOVs: 1790085 -> 1786768 (-0.19%); split: -0.19%, +0.00%
Full: 2156693 -> 2156607 (-0.00%); split: -0.00%, +0.00%
(ss): 1329812 -> 1329546 (-0.02%); split: -0.03%, +0.01%
(sy): 686396 -> 686386 (-0.00%); split: -0.00%, +0.00%
(ss)-stall: 4995295 -> 4995185 (-0.00%); split: -0.02%, +0.01%
(sy)-stall: 19828966 -> 19828624 (-0.00%); split: -0.01%, +0.01%
Cat0: 10450369 -> 10451731 (+0.01%); split: -0.00%, +0.02%
Cat1: 2787946 -> 2784566 (-0.12%); split: -0.12%, +0.00%
Cat2: 21265787 -> 21264447 (-0.01%)
Cat3: 16207098 -> 16206536 (-0.00%)
Cat7: 1597849 -> 1597840 (-0.00%); split: -0.00%, +0.00%

Totals from 730 (0.36% of 200220) affected shaders:
MaxWaves: 6308 -> 6354 (+0.73%); split: +0.79%, -0.06%
Instrs: 258235 -> 254306 (-1.52%); split: -1.59%, +0.07%
CodeSize: 698806 -> 703942 (+0.73%); split: -0.28%, +1.02%
NOPs: 21040 -> 22402 (+6.47%); split: -1.85%, +8.33%
MOVs: 9426 -> 6109 (-35.19%); split: -35.52%, +0.33%
Full: 8914 -> 8828 (-0.96%); split: -1.03%, +0.07%
(ss): 5118 -> 4852 (-5.20%); split: -6.58%, +1.39%
(sy): 2118 -> 2108 (-0.47%); split: -1.18%, +0.71%
(ss)-stall: 17360 -> 17250 (-0.63%); split: -4.57%, +3.94%
(sy)-stall: 34921 -> 34579 (-0.98%); split: -5.90%, +4.92%
Cat0: 24734 -> 26096 (+5.51%); split: -1.58%, +7.09%
Cat1: 12311 -> 8931 (-27.46%); split: -27.70%, +0.24%
Cat2: 106329 -> 104989 (-1.26%)
Cat3: 100547 -> 99985 (-0.56%)
Cat7: 3646 -> 3637 (-0.25%); split: -0.91%, +0.66%

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34279>
This commit is contained in:
Job Noorman 2025-03-30 11:42:39 +02:00 • committed by Marge Bot
parent 7959250d1e
commit 78ef51aa04
1 changed files with 21 additions and 4 deletions
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25
src/freedreno/ir3/ir3_nir_opt_preamble.c
View file

@ -212,6 +212,8 @@ instr_cost(nir_instr *instr, const void *data)
static float
rewrite_cost(nir_def *def, const void *data)
{
const struct ir3_shader_variant *v = data;
/* We always have to expand booleans */
if (def->bit_size == 1)
return def->num_components;
@ -219,10 +221,7 @@ rewrite_cost(nir_def *def, const void *data)
bool mov_needed = false;
nir_foreach_use (use, def) {
nir_instr *parent_instr = nir_src_parent_instr(use);
if (parent_instr->type != nir_instr_type_alu) {
mov_needed = true;
break;
} else {
if (parent_instr->type == nir_instr_type_alu) {
nir_alu_instr *alu = nir_instr_as_alu(parent_instr);
if (alu->op == nir_op_vec2 ||
alu->op == nir_op_vec3 ||
@ -233,6 +232,23 @@ rewrite_cost(nir_def *def, const void *data)
} else {
/* Assume for non-moves that the const is folded into the src */
}
} else if (parent_instr->type == nir_instr_type_intrinsic) {
nir_intrinsic_instr *parent_intrin =
nir_instr_as_intrinsic(parent_instr);
if (v->compiler->has_alias_rt && v->type == MESA_SHADER_FRAGMENT &&
parent_intrin->intrinsic == nir_intrinsic_store_output &&
def->bit_size == 32) {
/* For FS outputs, alias.rt can use const registers without a mov.
* This only works for full regs though.
*/
} else {
mov_needed = true;
break;
}
} else {
mov_needed = true;
break;
}
}
@ -307,6 +323,7 @@ ir3_nir_opt_preamble(nir_shader *nir, struct ir3_shader_variant *v)
.instr_cost_cb = instr_cost,
.avoid_instr_cb = avoid_instr,
.rewrite_cost_cb = rewrite_cost,
.cb_data = v,
};
unsigned size = 0;