From 78e5157a9cf7adb523f77f655afabcbc4b51b08e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tapani=20P=C3=A4lli?= <tapani.palli@intel.com>
Date: Wed, 26 Feb 2025 09:46:58 +0200
Subject: [PATCH] intel/compiler: add a spec note about L1WT types being
 uncached
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Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33755>
---
 src/intel/compiler/brw_eu_defines.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index 63bf0bc4181..66b8ca9f56b 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -1721,6 +1721,9 @@ enum PACKED xe2_lsc_cache_store {
    XE2_LSC_CACHE_STORE_L1UC_L3UC = 2,
    /* Override to L1 uncached and L3 cached */
    XE2_LSC_CACHE_STORE_L1UC_L3WB = 4,
+   /* From BSpec: 71167 for L1WT_L3UC and L1WT_L3WB:
+    * "L1 will be uncached rather than write-through."
+    */
    /* Override to L1 write-through and L3 uncached */
    XE2_LSC_CACHE_STORE_L1WT_L3UC = 6,
    /* Override to L1 write-through and L3 cached */