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ir3/shared_ra: fix live-out reload after src reload
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When reloading live-out values along loop back-edges, we make sure to
reuse the original register. However, we failed to detect cases where
the spilled value got reloaded earlier for a src in a different
register. Fix this by reloading the value again in the original
register.

Fixes a RA validation failure in Windrose.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: fa22b0901a ("ir3/ra: Add specialized shared register RA/spilling")
(cherry picked from commit aaf4d77f43)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41269>
This commit is contained in:
Job Noorman 2026-04-29 14:13:07 +02:00 • committed by Eric Engestrom
parent ac3699b9b7
commit 78d55d6009
2 changed files with 4 additions and 2 deletions
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2
.pick_status.json
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@ -14,7 +14,7 @@
"description": "ir3/shared_ra: fix live-out reload after src reload",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "fa22b0901af548d5e1433ad4cdbda314182137c5",
"notes": null

4
src/freedreno/ir3/ir3_shared_ra.c
View file

@ -1246,7 +1246,9 @@ reload_live_outs(struct ra_ctx *ctx, struct ir3_block *block)
struct ir3_register *reg = ctx->live->definitions[name];
struct ra_interval *interval = &ctx->intervals[name];
if (!interval->interval.inserted) {
if (!interval->interval.inserted ||
(interval->spill_def &&
interval->physreg_start != interval->physreg_start_orig)) {
d("reloading %d at end of backedge", reg->name);
/* When this interval was spilled inside the loop, we probably chose a