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radv/meta: rename more buffer->memory for fill/copy/update operations

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Recently, I renamed most of the helpers for future work but I forgot
few things like meta keys, etc.

This is for consistency.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34558>
This commit is contained in:
Samuel Pitoiset 2025-04-09 11:58:44 +02:00
parent 43c8cb1ae2
commit 78c2feed00
6 changed files with 23 additions and 23 deletions
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6
src/amd/vulkan/meta/radv_meta.h
View file

@ -78,8 +78,8 @@ enum radv_meta_object_key_type {
RADV_META_OBJECT_KEY_BLIT2D_COLOR, RADV_META_OBJECT_KEY_BLIT2D_COLOR,
RADV_META_OBJECT_KEY_BLIT2D_DEPTH, RADV_META_OBJECT_KEY_BLIT2D_DEPTH,
RADV_META_OBJECT_KEY_BLIT2D_STENCIL, RADV_META_OBJECT_KEY_BLIT2D_STENCIL,
RADV_META_OBJECT_KEY_FILL_BUFFER, RADV_META_OBJECT_KEY_FILL_MEMORY,
RADV_META_OBJECT_KEY_COPY_BUFFER, RADV_META_OBJECT_KEY_COPY_MEMORY,
RADV_META_OBJECT_KEY_COPY_IMAGE_TO_BUFFER, RADV_META_OBJECT_KEY_COPY_IMAGE_TO_BUFFER,
RADV_META_OBJECT_KEY_COPY_BUFFER_TO_IMAGE, RADV_META_OBJECT_KEY_COPY_BUFFER_TO_IMAGE,
RADV_META_OBJECT_KEY_COPY_BUFFER_TO_IMAGE_R32G32B32, RADV_META_OBJECT_KEY_COPY_BUFFER_TO_IMAGE_R32G32B32,
@ -218,7 +218,7 @@ uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *i
uint32_t radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image, uint32_t radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image,
const VkImageSubresourceRange *range, uint32_t value, bool is_clear); const VkImageSubresourceRange *range, uint32_t value, bool is_clear);
void radv_update_buffer_cp(struct radv_cmd_buffer *cmd_buffer, uint64_t va, const void *data, uint64_t size); void radv_update_memory_cp(struct radv_cmd_buffer *cmd_buffer, uint64_t va, const void *data, uint64_t size);
void radv_meta_decode_etc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, VkImageLayout layout, void radv_meta_decode_etc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, VkImageLayout layout,
const VkImageSubresourceLayers *subresource, VkOffset3D offset, VkExtent3D extent); const VkImageSubresourceLayers *subresource, VkOffset3D offset, VkExtent3D extent);

20
src/amd/vulkan/meta/radv_meta_buffer.c
View file

@ -23,9 +23,9 @@ struct fill_constants {
}; };
static VkResult static VkResult
get_fill_pipeline(struct radv_device *device, VkPipeline *pipeline_out, VkPipelineLayout *layout_out) get_fill_memory_pipeline(struct radv_device *device, VkPipeline *pipeline_out, VkPipelineLayout *layout_out)
{ {
enum radv_meta_object_key_type key = RADV_META_OBJECT_KEY_FILL_BUFFER; enum radv_meta_object_key_type key = RADV_META_OBJECT_KEY_FILL_MEMORY;
VkResult result; VkResult result;
const VkPushConstantRange pc_range = { const VkPushConstantRange pc_range = {
@ -44,7 +44,7 @@ get_fill_pipeline(struct radv_device *device, VkPipeline *pipeline_out, VkPipeli
return VK_SUCCESS; return VK_SUCCESS;
} }
nir_shader *cs = radv_meta_nir_build_buffer_fill_shader(device); nir_shader *cs = radv_meta_nir_build_fill_memory_shader(device);
const VkPipelineShaderStageCreateInfo stage_info = { const VkPipelineShaderStageCreateInfo stage_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@ -75,9 +75,9 @@ struct copy_constants {
}; };
static VkResult static VkResult
get_copy_pipeline(struct radv_device *device, VkPipeline *pipeline_out, VkPipelineLayout *layout_out) get_copy_memory_pipeline(struct radv_device *device, VkPipeline *pipeline_out, VkPipelineLayout *layout_out)
{ {
enum radv_meta_object_key_type key = RADV_META_OBJECT_KEY_COPY_BUFFER; enum radv_meta_object_key_type key = RADV_META_OBJECT_KEY_COPY_MEMORY;
VkResult result; VkResult result;
const VkPushConstantRange pc_range = { const VkPushConstantRange pc_range = {
@ -96,7 +96,7 @@ get_copy_pipeline(struct radv_device *device, VkPipeline *pipeline_out, VkPipeli
return VK_SUCCESS; return VK_SUCCESS;
} }
nir_shader *cs = radv_meta_nir_build_buffer_copy_shader(device); nir_shader *cs = radv_meta_nir_build_copy_memory_shader(device);
const VkPipelineShaderStageCreateInfo stage_info = { const VkPipelineShaderStageCreateInfo stage_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@ -129,7 +129,7 @@ radv_compute_fill_memory(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64
VkPipeline pipeline; VkPipeline pipeline;
VkResult result; VkResult result;
result = get_fill_pipeline(device, &pipeline, &layout); result = get_fill_memory_pipeline(device, &pipeline, &layout);
if (result != VK_SUCCESS) { if (result != VK_SUCCESS) {
vk_command_buffer_set_error(&cmd_buffer->vk, result); vk_command_buffer_set_error(&cmd_buffer->vk, result);
return; return;
@ -164,7 +164,7 @@ radv_compute_copy_memory(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, ui
VkPipeline pipeline; VkPipeline pipeline;
VkResult result; VkResult result;
result = get_copy_pipeline(device, &pipeline, &layout); result = get_copy_memory_pipeline(device, &pipeline, &layout);
if (result != VK_SUCCESS) { if (result != VK_SUCCESS) {
vk_command_buffer_set_error(&cmd_buffer->vk, result); vk_command_buffer_set_error(&cmd_buffer->vk, result);
return; return;
@ -335,7 +335,7 @@ radv_CmdCopyBuffer2(VkCommandBuffer commandBuffer, const VkCopyBufferInfo2 *pCop
} }
void void
radv_update_buffer_cp(struct radv_cmd_buffer *cmd_buffer, uint64_t va, const void *data, uint64_t size) radv_update_memory_cp(struct radv_cmd_buffer *cmd_buffer, uint64_t va, const void *data, uint64_t size)
{ {
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer); struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
uint64_t words = size / 4; uint64_t words = size / 4;
@ -369,7 +369,7 @@ radv_update_memory(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t siz
return; return;
if (size < RADV_BUFFER_UPDATE_THRESHOLD && cmd_buffer->qf != RADV_QUEUE_TRANSFER) { if (size < RADV_BUFFER_UPDATE_THRESHOLD && cmd_buffer->qf != RADV_QUEUE_TRANSFER) {
radv_update_buffer_cp(cmd_buffer, va, data, size); radv_update_memory_cp(cmd_buffer, va, data, size);
} else { } else {
enum radv_copy_flags src_copy_flags = 0; enum radv_copy_flags src_copy_flags = 0;
uint32_t buf_offset; uint32_t buf_offset;

4
src/amd/vulkan/nir/radv_meta_nir.c
View file

@ -123,7 +123,7 @@ radv_meta_nir_break_on_count(nir_builder *b, nir_variable *var, nir_def *count)
} }
nir_shader * nir_shader *
radv_meta_nir_build_buffer_fill_shader(struct radv_device *dev) radv_meta_nir_build_fill_memory_shader(struct radv_device *dev)
{ {
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_buffer_fill"); nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_buffer_fill");
b.shader->info.workgroup_size[0] = 64; b.shader->info.workgroup_size[0] = 64;
@ -145,7 +145,7 @@ radv_meta_nir_build_buffer_fill_shader(struct radv_device *dev)
} }
nir_shader * nir_shader *
radv_meta_nir_build_buffer_copy_shader(struct radv_device *dev) radv_meta_nir_build_copy_memory_shader(struct radv_device *dev)
{ {
nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_buffer_copy"); nir_builder b = radv_meta_nir_init_shader(dev, MESA_SHADER_COMPUTE, "meta_buffer_copy");
b.shader->info.workgroup_size[0] = 64; b.shader->info.workgroup_size[0] = 64;

4
src/amd/vulkan/nir/radv_meta_nir.h
View file

@ -31,8 +31,8 @@ nir_def *radv_meta_nir_get_global_ids(nir_builder *b, unsigned num_components);
void radv_meta_nir_break_on_count(nir_builder *b, nir_variable *var, nir_def *count); void radv_meta_nir_break_on_count(nir_builder *b, nir_variable *var, nir_def *count);
nir_shader *radv_meta_nir_build_buffer_fill_shader(struct radv_device *dev); nir_shader *radv_meta_nir_build_fill_memory_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_buffer_copy_shader(struct radv_device *dev); nir_shader *radv_meta_nir_build_copy_memory_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_blit_vertex_shader(struct radv_device *dev); nir_shader *radv_meta_nir_build_blit_vertex_shader(struct radv_device *dev);
nir_shader *radv_meta_nir_build_blit_copy_fragment_shader(struct radv_device *dev, enum glsl_sampler_dim tex_dim); nir_shader *radv_meta_nir_build_blit_copy_fragment_shader(struct radv_device *dev, enum glsl_sampler_dim tex_dim);

10
src/amd/vulkan/radv_acceleration_structure.c
View file

@ -502,7 +502,7 @@ radv_encode_as(VkCommandBuffer commandBuffer, const VkAccelerationStructureBuild
if (key & RADV_ENCODE_KEY_COMPACT) { if (key & RADV_ENCODE_KEY_COMPACT) {
uint32_t dst_offset = layout.internal_nodes_offset - layout.bvh_offset; uint32_t dst_offset = layout.internal_nodes_offset - layout.bvh_offset;
radv_update_buffer_cp(cmd_buffer, intermediate_header_addr + offsetof(struct vk_ir_header, dst_node_offset), radv_update_memory_cp(cmd_buffer, intermediate_header_addr + offsetof(struct vk_ir_header, dst_node_offset),
&dst_offset, sizeof(uint32_t)); &dst_offset, sizeof(uint32_t));
if (radv_device_physical(device)->info.cp_sdma_ge_use_system_memory_scope) if (radv_device_physical(device)->info.cp_sdma_ge_use_system_memory_scope)
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_L2; cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_L2;
@ -552,7 +552,7 @@ radv_encode_as_gfx12(VkCommandBuffer commandBuffer, const VkAccelerationStructur
}; };
const uint8_t *update_data = ((const uint8_t *)&header + offsetof(struct vk_ir_header, sync_data)); const uint8_t *update_data = ((const uint8_t *)&header + offsetof(struct vk_ir_header, sync_data));
radv_update_buffer_cp(cmd_buffer, intermediate_header_addr + offsetof(struct vk_ir_header, sync_data), update_data, radv_update_memory_cp(cmd_buffer, intermediate_header_addr + offsetof(struct vk_ir_header, sync_data), update_data,
sizeof(struct vk_ir_header) - offsetof(struct vk_ir_header, sync_data)); sizeof(struct vk_ir_header) - offsetof(struct vk_ir_header, sync_data));
if (radv_device_physical(device)->info.cp_sdma_ge_use_system_memory_scope) if (radv_device_physical(device)->info.cp_sdma_ge_use_system_memory_scope)
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_L2; cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_INV_L2;
@ -656,7 +656,7 @@ radv_init_header(VkCommandBuffer commandBuffer, const VkAccelerationStructureBui
header.geometry_count = build_info->geometryCount; header.geometry_count = build_info->geometryCount;
header.primitive_base_indices_offset = layout.primitive_base_indices_offset; header.primitive_base_indices_offset = layout.primitive_base_indices_offset;
radv_update_buffer_cp(cmd_buffer, vk_acceleration_structure_get_va(dst) + base, (const char *)&header + base, radv_update_memory_cp(cmd_buffer, vk_acceleration_structure_get_va(dst) + base, (const char *)&header + base,
sizeof(header) - base); sizeof(header) - base);
if (device->rra_trace.accel_structs) { if (device->rra_trace.accel_structs) {
@ -810,7 +810,7 @@ static void
radv_write_buffer_cp(VkCommandBuffer commandBuffer, VkDeviceAddress addr, void *data, uint32_t size) radv_write_buffer_cp(VkCommandBuffer commandBuffer, VkDeviceAddress addr, void *data, uint32_t size)
{ {
VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
radv_update_buffer_cp(cmd_buffer, addr, data, size); radv_update_memory_cp(cmd_buffer, addr, data, size);
} }
static void static void
@ -1157,5 +1157,5 @@ radv_CmdCopyAccelerationStructureToMemoryKHR(VkCommandBuffer commandBuffer,
memcpy(header_data, pdev->driver_uuid, VK_UUID_SIZE); memcpy(header_data, pdev->driver_uuid, VK_UUID_SIZE);
memcpy(header_data + VK_UUID_SIZE, pdev->cache_uuid, VK_UUID_SIZE); memcpy(header_data + VK_UUID_SIZE, pdev->cache_uuid, VK_UUID_SIZE);
radv_update_buffer_cp(cmd_buffer, pInfo->dst.deviceAddress, header_data, sizeof(header_data)); radv_update_memory_cp(cmd_buffer, pInfo->dst.deviceAddress, header_data, sizeof(header_data));
} }

2
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -12631,7 +12631,7 @@ radv_trace_trace_rays(struct radv_cmd_buffer *cmd_buffer, const VkTraceRaysIndir
radv_dst_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT, radv_dst_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT,
VK_ACCESS_2_SHADER_READ_BIT, 0, NULL, NULL); VK_ACCESS_2_SHADER_READ_BIT, 0, NULL, NULL);
radv_update_buffer_cp(cmd_buffer, radv_update_memory_cp(cmd_buffer,
device->rra_trace.ray_history_addr + offsetof(struct radv_ray_history_header, dispatch_index), device->rra_trace.ray_history_addr + offsetof(struct radv_ray_history_header, dispatch_index),
&dispatch_index, sizeof(dispatch_index)); &dispatch_index, sizeof(dispatch_index));
} }