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i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK

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Fixes the following tests on CHV, BXT, and GLK:
    KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot
    dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103115

(cherry picked from commit cfcfa0b9cd)
This commit is contained in:
Matt Turner 2017-11-08 15:14:19 -08:00 • committed by Emil Velikov
parent 3be7bb6741
commit 78a7e2a2d4
1 changed files with 4 additions and 4 deletions
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8
src/intel/compiler/brw_fs_nir.cpp
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@ -635,8 +635,12 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
break;
case nir_op_f2f64:
case nir_op_f2i64:
case nir_op_f2u64:
case nir_op_i2f64:
case nir_op_i2i64:
case nir_op_u2f64:
case nir_op_u2u64:
/* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
*
* "When source or destination is 64b (...), regioning in Align1
@ -664,12 +668,8 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
case nir_op_f2f32:
case nir_op_f2i32:
case nir_op_f2u32:
case nir_op_f2i64:
case nir_op_f2u64:
case nir_op_i2i32:
case nir_op_i2i64:
case nir_op_u2u32:
case nir_op_u2u64:
inst = bld.MOV(result, op[0]);
inst->saturate = instr->dest.saturate;
break;