mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-27 23:30:10 +01:00
aco: add reg() helper to assembler
SGPR encoding is slightly different on GFX11. Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17333>
This commit is contained in:
Rhys Perry
Marge Bot
parent
7a1b522148
commit
78779fd63d
1 changed files with 99 additions and 82 deletions
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@ -72,6 +72,24 @@ get_mimg_nsa_dwords(const Instruction* instr)
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return 0;
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}
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uint32_t
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reg(asm_context& ctx, PhysReg reg)
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{
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return reg.reg();
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}
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ALWAYS_INLINE uint32_t
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reg(asm_context& ctx, Operand op, unsigned width = 32)
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{
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return reg(ctx, op.physReg()) & BITFIELD_MASK(width);
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}
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ALWAYS_INLINE uint32_t
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reg(asm_context& ctx, Definition def, unsigned width = 32)
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{
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return reg(ctx, def.physReg()) & BITFIELD_MASK(width);
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}
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void
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emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* instr)
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{
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@ -113,9 +131,9 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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case Format::SOP2: {
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uint32_t encoding = (0b10 << 30);
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encoding |= opcode << 23;
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encoding |= !instr->definitions.empty() ? instr->definitions[0].physReg() << 16 : 0;
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encoding |= instr->operands.size() >= 2 ? instr->operands[1].physReg() << 8 : 0;
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encoding |= !instr->operands.empty() ? instr->operands[0].physReg() : 0;
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encoding |= !instr->definitions.empty() ? reg(ctx, instr->definitions[0]) << 16 : 0;
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encoding |= instr->operands.size() >= 2 ? reg(ctx, instr->operands[1]) << 8 : 0;
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encoding |= !instr->operands.empty() ? reg(ctx, instr->operands[0]) : 0;
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out.push_back(encoding);
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break;
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}
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@ -139,9 +157,9 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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uint32_t encoding = (0b1011 << 28);
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encoding |= opcode << 23;
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encoding |= !instr->definitions.empty() && !(instr->definitions[0].physReg() == scc)
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? instr->definitions[0].physReg() << 16
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? reg(ctx, instr->definitions[0]) << 16
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: !instr->operands.empty() && instr->operands[0].physReg() <= 127
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? instr->operands[0].physReg() << 16
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? reg(ctx, instr->operands[0]) << 16
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: 0;
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encoding |= sopk.imm;
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out.push_back(encoding);
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@ -149,17 +167,17 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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}
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case Format::SOP1: {
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uint32_t encoding = (0b101111101 << 23);
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encoding |= !instr->definitions.empty() ? instr->definitions[0].physReg() << 16 : 0;
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encoding |= !instr->definitions.empty() ? reg(ctx, instr->definitions[0]) << 16 : 0;
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encoding |= opcode << 8;
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encoding |= !instr->operands.empty() ? instr->operands[0].physReg() : 0;
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encoding |= !instr->operands.empty() ? reg(ctx, instr->operands[0]) : 0;
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out.push_back(encoding);
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break;
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}
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case Format::SOPC: {
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uint32_t encoding = (0b101111110 << 23);
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encoding |= opcode << 16;
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encoding |= instr->operands.size() == 2 ? instr->operands[1].physReg() << 8 : 0;
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encoding |= !instr->operands.empty() ? instr->operands[0].physReg() : 0;
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encoding |= instr->operands.size() == 2 ? reg(ctx, instr->operands[1]) << 8 : 0;
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encoding |= !instr->operands.empty() ? reg(ctx, instr->operands[0]) : 0;
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out.push_back(encoding);
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break;
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}
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@ -184,11 +202,11 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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if (ctx.gfx_level <= GFX7) {
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encoding = (0b11000 << 27);
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encoding |= opcode << 22;
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encoding |= instr->definitions.size() ? instr->definitions[0].physReg() << 15 : 0;
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encoding |= instr->operands.size() ? (instr->operands[0].physReg() >> 1) << 9 : 0;
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encoding |= instr->definitions.size() ? reg(ctx, instr->definitions[0]) << 15 : 0;
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encoding |= instr->operands.size() ? (reg(ctx, instr->operands[0]) >> 1) << 9 : 0;
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if (instr->operands.size() >= 2) {
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if (!instr->operands[1].isConstant()) {
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encoding |= instr->operands[1].physReg().reg();
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encoding |= reg(ctx, instr->operands[1]);
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} else if (instr->operands[1].constantValue() >= 1024) {
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encoding |= 255; /* SQ_SRC_LITERAL */
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} else {
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@ -226,32 +244,33 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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}
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if (is_load || instr->operands.size() >= 3) { /* SDATA */
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encoding |= (is_load ? instr->definitions[0].physReg() : instr->operands[2].physReg())
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encoding |= (is_load ? reg(ctx, instr->definitions[0]) : reg(ctx, instr->operands[2]))
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<< 6;
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}
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if (instr->operands.size() >= 1) { /* SBASE */
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encoding |= instr->operands[0].physReg() >> 1;
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encoding |= reg(ctx, instr->operands[0]) >> 1;
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}
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out.push_back(encoding);
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encoding = 0;
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int32_t offset = 0;
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uint32_t soffset = ctx.gfx_level >= GFX10
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? sgpr_null /* On GFX10 this is disabled by specifying SGPR_NULL */
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: 0; /* On GFX9, it is disabled by the SOE bit (and it's not present on
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GFX8 and below) */
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uint32_t soffset =
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ctx.gfx_level >= GFX10
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? reg(ctx, sgpr_null) /* On GFX10 this is disabled by specifying SGPR_NULL */
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: 0; /* On GFX9, it is disabled by the SOE bit (and it's not present on
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GFX8 and below) */
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if (instr->operands.size() >= 2) {
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const Operand& op_off1 = instr->operands[1];
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if (ctx.gfx_level <= GFX9) {
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offset = op_off1.isConstant() ? op_off1.constantValue() : op_off1.physReg();
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offset = op_off1.isConstant() ? op_off1.constantValue() : reg(ctx, op_off1);
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} else {
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/* GFX10 only supports constants in OFFSET, so put the operand in SOFFSET if it's an
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* SGPR */
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if (op_off1.isConstant()) {
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offset = op_off1.constantValue();
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} else {
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soffset = op_off1.physReg();
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soffset = reg(ctx, op_off1);
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assert(!soe); /* There is no place to put the other SGPR offset, if any */
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}
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}
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@ -261,7 +280,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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assert(ctx.gfx_level >= GFX9); /* GFX8 and below don't support specifying a constant
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and an SGPR at the same time */
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assert(!op_off2.isConstant());
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soffset = op_off2.physReg();
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soffset = reg(ctx, op_off2);
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}
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}
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encoding |= offset;
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@ -273,27 +292,27 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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case Format::VOP2: {
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uint32_t encoding = 0;
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encoding |= opcode << 25;
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encoding |= (0xFF & instr->definitions[0].physReg()) << 17;
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encoding |= (0xFF & instr->operands[1].physReg()) << 9;
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encoding |= instr->operands[0].physReg();
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encoding |= reg(ctx, instr->definitions[0], 8) << 17;
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encoding |= reg(ctx, instr->operands[1], 8) << 9;
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encoding |= reg(ctx, instr->operands[0]);
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out.push_back(encoding);
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break;
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}
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case Format::VOP1: {
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uint32_t encoding = (0b0111111 << 25);
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if (!instr->definitions.empty())
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encoding |= (0xFF & instr->definitions[0].physReg()) << 17;
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encoding |= reg(ctx, instr->definitions[0], 8) << 17;
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encoding |= opcode << 9;
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if (!instr->operands.empty())
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encoding |= instr->operands[0].physReg();
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encoding |= reg(ctx, instr->operands[0]);
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out.push_back(encoding);
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break;
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}
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case Format::VOPC: {
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uint32_t encoding = (0b0111110 << 25);
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encoding |= opcode << 17;
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encoding |= (0xFF & instr->operands[1].physReg()) << 9;
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encoding |= instr->operands[0].physReg();
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encoding |= reg(ctx, instr->operands[1], 8) << 9;
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encoding |= reg(ctx, instr->operands[0]);
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out.push_back(encoding);
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break;
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}
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@ -314,17 +333,17 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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}
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encoding |= opcode << 16;
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encoding |= (0xFF & instr->definitions[0].physReg());
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encoding |= reg(ctx, instr->definitions[0], 8);
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out.push_back(encoding);
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encoding = 0;
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encoding |= interp.attribute;
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encoding |= interp.component << 6;
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encoding |= instr->operands[0].physReg() << 9;
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encoding |= reg(ctx, instr->operands[0]) << 9;
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if (instr->opcode == aco_opcode::v_interp_p2_f16 ||
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instr->opcode == aco_opcode::v_interp_p2_legacy_f16 ||
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instr->opcode == aco_opcode::v_interp_p1lv_f16) {
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encoding |= instr->operands[2].physReg() << 18;
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encoding |= reg(ctx, instr->operands[2]) << 18;
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}
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out.push_back(encoding);
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} else {
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@ -335,14 +354,14 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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}
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assert(encoding);
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encoding |= (0xFF & instr->definitions[0].physReg()) << 18;
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encoding |= reg(ctx, instr->definitions[0], 8) << 18;
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encoding |= opcode << 16;
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encoding |= interp.attribute << 10;
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encoding |= interp.component << 8;
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if (instr->opcode == aco_opcode::v_interp_mov_f32)
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encoding |= (0x3 & instr->operands[0].constantValue());
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else
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encoding |= (0xFF & instr->operands[0].physReg());
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encoding |= reg(ctx, instr->operands[0], 8);
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out.push_back(encoding);
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}
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break;
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@ -361,17 +380,13 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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encoding |= (0xFFFF & ds.offset0);
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out.push_back(encoding);
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encoding = 0;
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unsigned reg = !instr->definitions.empty() ? instr->definitions[0].physReg() : 0;
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encoding |= (0xFF & reg) << 24;
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reg = instr->operands.size() >= 3 && !(instr->operands[2].physReg() == m0)
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? instr->operands[2].physReg()
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: 0;
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encoding |= (0xFF & reg) << 16;
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reg = instr->operands.size() >= 2 && !(instr->operands[1].physReg() == m0)
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? instr->operands[1].physReg()
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: 0;
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encoding |= (0xFF & reg) << 8;
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encoding |= (0xFF & instr->operands[0].physReg());
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if (!instr->definitions.empty())
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encoding |= reg(ctx, instr->definitions[0], 8) << 24;
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if (instr->operands.size() >= 3 && instr->operands[2].physReg() != m0)
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encoding |= reg(ctx, instr->operands[2], 8) << 16;
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if (instr->operands.size() >= 2 && instr->operands[1].physReg() != m0)
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encoding |= reg(ctx, instr->operands[1], 8) << 8;
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encoding |= reg(ctx, instr->operands[0], 8);
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out.push_back(encoding);
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break;
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}
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@ -398,13 +413,14 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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if (ctx.gfx_level <= GFX7 || ctx.gfx_level >= GFX10) {
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encoding |= (mubuf.slc ? 1 : 0) << 22;
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}
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encoding |= instr->operands[2].physReg() << 24;
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encoding |= reg(ctx, instr->operands[2]) << 24;
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encoding |= (mubuf.tfe ? 1 : 0) << 23;
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encoding |= (instr->operands[0].physReg() >> 2) << 16;
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unsigned reg = instr->operands.size() > 3 ? instr->operands[3].physReg()
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: instr->definitions[0].physReg();
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encoding |= (0xFF & reg) << 8;
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encoding |= (0xFF & instr->operands[1].physReg());
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encoding |= (reg(ctx, instr->operands[0]) >> 2) << 16;
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if (instr->operands.size() > 3)
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encoding |= reg(ctx, instr->operands[3], 8) << 8;
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else
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encoding |= reg(ctx, instr->definitions[0], 8) << 8;
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encoding |= reg(ctx, instr->operands[1], 8);
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out.push_back(encoding);
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break;
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}
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@ -431,14 +447,15 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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out.push_back(encoding);
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encoding = 0;
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encoding |= instr->operands[2].physReg() << 24;
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encoding |= reg(ctx, instr->operands[2]) << 24;
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encoding |= (mtbuf.tfe ? 1 : 0) << 23;
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encoding |= (mtbuf.slc ? 1 : 0) << 22;
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encoding |= (instr->operands[0].physReg() >> 2) << 16;
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unsigned reg = instr->operands.size() > 3 ? instr->operands[3].physReg()
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: instr->definitions[0].physReg();
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encoding |= (0xFF & reg) << 8;
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encoding |= (0xFF & instr->operands[1].physReg());
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encoding |= (reg(ctx, instr->operands[0]) >> 2) << 16;
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if (instr->operands.size() > 3)
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encoding |= reg(ctx, instr->operands[3], 8) << 8;
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else
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encoding |= reg(ctx, instr->definitions[0], 8) << 8;
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encoding |= reg(ctx, instr->operands[1], 8);
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if (ctx.gfx_level >= GFX10) {
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encoding |= (((opcode & 0x08) >> 3) << 21); /* MSB of 4-bit OPCODE */
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@ -474,15 +491,15 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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}
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encoding |= (0xF & mimg.dmask) << 8;
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out.push_back(encoding);
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encoding = (0xFF & instr->operands[3].physReg()); /* VADDR */
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encoding = reg(ctx, instr->operands[3], 8); /* VADDR */
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if (!instr->definitions.empty()) {
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encoding |= (0xFF & instr->definitions[0].physReg()) << 8; /* VDATA */
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encoding |= reg(ctx, instr->definitions[0], 8) << 8; /* VDATA */
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} else if (!instr->operands[2].isUndefined()) {
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encoding |= (0xFF & instr->operands[2].physReg()) << 8; /* VDATA */
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encoding |= reg(ctx, instr->operands[2], 8) << 8; /* VDATA */
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}
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encoding |= (0x1F & (instr->operands[0].physReg() >> 2)) << 16; /* T# (resource) */
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encoding |= (0x1F & (reg(ctx, instr->operands[0]) >> 2)) << 16; /* T# (resource) */
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if (!instr->operands[1].isUndefined())
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encoding |= (0x1F & (instr->operands[1].physReg() >> 2)) << 21; /* sampler */
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encoding |= (0x1F & (reg(ctx, instr->operands[1]) >> 2)) << 21; /* sampler */
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assert(!mimg.d16 || ctx.gfx_level >= GFX9);
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encoding |= mimg.d16 ? 1 << 31 : 0;
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@ -497,7 +514,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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out.resize(out.size() + nsa_dwords);
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std::vector<uint32_t>::iterator nsa = std::prev(out.end(), nsa_dwords);
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for (unsigned i = 0; i < instr->operands.size() - 4u; i++)
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nsa[i / 4] |= (0xFF & instr->operands[4 + i].physReg().reg()) << (i % 4 * 8);
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nsa[i / 4] |= reg(ctx, instr->operands[4 + i], 8) << (i % 4 * 8);
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}
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break;
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}
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@ -536,15 +553,15 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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assert(!flat.dlc);
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}
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out.push_back(encoding);
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encoding = (0xFF & instr->operands[0].physReg());
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encoding = reg(ctx, instr->operands[0], 8);
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if (!instr->definitions.empty())
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encoding |= (0xFF & instr->definitions[0].physReg()) << 24;
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encoding |= reg(ctx, instr->definitions[0], 8) << 24;
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if (instr->operands.size() >= 3)
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encoding |= (0xFF & instr->operands[2].physReg()) << 8;
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encoding |= reg(ctx, instr->operands[2], 8) << 8;
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if (!instr->operands[1].isUndefined()) {
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assert(ctx.gfx_level >= GFX10 || instr->operands[1].physReg() != 0x7F);
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assert(instr->format != Format::FLAT);
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encoding |= instr->operands[1].physReg() << 16;
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encoding |= reg(ctx, instr->operands[1], 8) << 16;
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} else if (instr->format != Format::FLAT ||
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ctx.gfx_level >= GFX10) { /* SADDR is actually used with FLAT on GFX10 */
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/* For GFX10.3 scratch, 0x7F disables both ADDR and SADDR, unlike sgpr_null, which only
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@ -554,7 +571,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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(instr->format == Format::SCRATCH && instr->operands[0].isUndefined()))
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encoding |= 0x7F << 16;
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else
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encoding |= sgpr_null << 16;
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encoding |= reg(ctx, sgpr_null) << 16;
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}
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encoding |= flat.nv ? 1 << 23 : 0;
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out.push_back(encoding);
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@ -575,10 +592,10 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
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encoding |= exp.dest << 4;
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encoding |= exp.enabled_mask;
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out.push_back(encoding);
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encoding = 0xFF & exp.operands[0].physReg();
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encoding |= (0xFF & exp.operands[1].physReg()) << 8;
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encoding |= (0xFF & exp.operands[2].physReg()) << 16;
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encoding |= (0xFF & exp.operands[3].physReg()) << 24;
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encoding = reg(ctx, exp.operands[0], 8);
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encoding |= reg(ctx, exp.operands[1], 8) << 8;
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encoding |= reg(ctx, exp.operands[2], 8) << 16;
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encoding |= reg(ctx, exp.operands[3], 8) << 24;
|
||||
out.push_back(encoding);
|
||||
break;
|
||||
}
|
||||
|
|
@ -629,19 +646,19 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
|
|||
if (instr->definitions.size() == 2 && instr->isVOPC())
|
||||
assert(ctx.gfx_level <= GFX9 && instr->definitions[1].physReg() == exec);
|
||||
else if (instr->definitions.size() == 2)
|
||||
encoding |= instr->definitions[1].physReg() << 8;
|
||||
encoding |= (0xFF & instr->definitions[0].physReg());
|
||||
encoding |= reg(ctx, instr->definitions[1]) << 8;
|
||||
encoding |= reg(ctx, instr->definitions[0], 8);
|
||||
out.push_back(encoding);
|
||||
encoding = 0;
|
||||
if (instr->opcode == aco_opcode::v_interp_mov_f32) {
|
||||
encoding = 0x3 & instr->operands[0].constantValue();
|
||||
} else if (instr->opcode == aco_opcode::v_writelane_b32_e64) {
|
||||
encoding |= instr->operands[0].physReg() << 0;
|
||||
encoding |= instr->operands[1].physReg() << 9;
|
||||
encoding |= reg(ctx, instr->operands[0]) << 0;
|
||||
encoding |= reg(ctx, instr->operands[1]) << 9;
|
||||
/* Encoding src2 works fine with hardware but breaks some disassemblers. */
|
||||
} else {
|
||||
for (unsigned i = 0; i < instr->operands.size(); i++)
|
||||
encoding |= instr->operands[i].physReg() << (i * 9);
|
||||
encoding |= reg(ctx, instr->operands[i]) << (i * 9);
|
||||
}
|
||||
encoding |= vop3.omod << 27;
|
||||
for (unsigned i = 0; i < 3; i++)
|
||||
|
|
@ -666,11 +683,11 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
|
|||
encoding |= ((vop3.opsel_hi & 0x4) ? 1 : 0) << 14;
|
||||
for (unsigned i = 0; i < 3; i++)
|
||||
encoding |= vop3.neg_hi[i] << (8 + i);
|
||||
encoding |= (0xFF & instr->definitions[0].physReg());
|
||||
encoding |= reg(ctx, instr->definitions[0], 8);
|
||||
out.push_back(encoding);
|
||||
encoding = 0;
|
||||
for (unsigned i = 0; i < instr->operands.size(); i++)
|
||||
encoding |= instr->operands[i].physReg() << (i * 9);
|
||||
encoding |= reg(ctx, instr->operands[i]) << (i * 9);
|
||||
encoding |= (vop3.opsel_hi & 0x3) << 27;
|
||||
for (unsigned i = 0; i < 3; i++)
|
||||
encoding |= vop3.neg_lo[i] << (29 + i);
|
||||
|
|
@ -695,7 +712,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
|
|||
encoding |= 1 << 18; /* set Fetch Inactive to match GFX9 behaviour */
|
||||
encoding |= dpp.bound_ctrl << 19;
|
||||
encoding |= dpp.dpp_ctrl << 8;
|
||||
encoding |= (0xFF) & dpp_op.physReg();
|
||||
encoding |= reg(ctx, dpp_op, 8);
|
||||
out.push_back(encoding);
|
||||
return;
|
||||
} else if (instr->isDPP8()) {
|
||||
|
|
@ -707,7 +724,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
|
|||
instr->operands[0] = Operand(PhysReg{234}, v1);
|
||||
instr->format = (Format)((uint16_t)instr->format & ~(uint16_t)Format::DPP8);
|
||||
emit_instruction(ctx, out, instr);
|
||||
uint32_t encoding = (0xFF) & dpp_op.physReg();
|
||||
uint32_t encoding = reg(ctx, dpp_op, 8);
|
||||
for (unsigned i = 0; i < 8; ++i)
|
||||
encoding |= dpp.lane_sel[i] << (8 + i * 3);
|
||||
out.push_back(encoding);
|
||||
|
|
@ -727,7 +744,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
|
|||
if (instr->isVOPC()) {
|
||||
if (instr->definitions[0].physReg() !=
|
||||
(ctx.gfx_level >= GFX10 && is_cmpx(instr->opcode) ? exec : vcc)) {
|
||||
encoding |= instr->definitions[0].physReg() << 8;
|
||||
encoding |= reg(ctx, instr->definitions[0]) << 8;
|
||||
encoding |= 1 << 15;
|
||||
}
|
||||
encoding |= (sdwa.clamp ? 1 : 0) << 13;
|
||||
|
|
@ -753,7 +770,7 @@ emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction* inst
|
|||
encoding |= sdwa.neg[1] << 28;
|
||||
}
|
||||
|
||||
encoding |= 0xFF & sdwa_op.physReg();
|
||||
encoding |= reg(ctx, sdwa_op, 8);
|
||||
encoding |= (sdwa_op.physReg() < 256) << 23;
|
||||
if (instr->operands.size() >= 2)
|
||||
encoding |= (instr->operands[1].physReg() < 256) << 31;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue