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i965/gen7-8: Set up early depth/stencil control appropriately for image load/store.

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v2: Store early fragment test mode in brw_wm_prog_data instead of
    getting it from core mesa data structures (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Francisco Jerez 2015-02-09 21:04:53 +02:00
parent ac7664e493
commit 786e0853be
6 changed files with 21 additions and 3 deletions
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1
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -466,6 +466,7 @@ struct brw_wm_prog_data {
uint8_t computed_depth_mode;
bool early_fragment_tests;
bool no_8;
bool dual_src_blend;
bool uses_pos_offset;

3
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -2384,6 +2384,9 @@ enum brw_wm_barycentric_interp_mode {
# define GEN7_WM_KILL_ENABLE (1 << 25)
# define GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT 23
# define GEN7_WM_USES_SOURCE_DEPTH (1 << 20)
# define GEN7_WM_EARLY_DS_CONTROL_NORMAL (0 << 21)
# define GEN7_WM_EARLY_DS_CONTROL_PSEXEC (1 << 21)
# define GEN7_WM_EARLY_DS_CONTROL_PREPS (2 << 21)
# define GEN7_WM_USES_SOURCE_W (1 << 19)
# define GEN7_WM_POSITION_ZW_PIXEL (0 << 17)
# define GEN7_WM_POSITION_ZW_CENTROID (2 << 17)

2
src/mesa/drivers/dri/i965/brw_wm.c
View file

@ -179,6 +179,8 @@ brw_codegen_wm_prog(struct brw_context *brw,
fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK);
prog_data.computed_depth_mode = computed_depth_mode(&fp->program);
prog_data.early_fragment_tests = fs && fs->EarlyFragmentTests;
/* Use ALT floating point mode for ARB programs so that 0^0 == 1. */
if (!prog)
prog_data.base.use_alt_mode = true;

6
src/mesa/drivers/dri/i965/gen7_wm_state.c
View file

@ -107,6 +107,12 @@ upload_wm_state(struct brw_context *brw)
dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK;
}
/* BRW_NEW_FS_PROG_DATA */
if (prog_data->early_fragment_tests)
dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
else if (prog_data->base.nr_image_params)
dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
/* _NEW_BUFFERS | _NEW_COLOR */
if (brw->is_haswell &&
!(brw_color_buffer_write_enabled(brw) || writes_depth) &&

6
src/mesa/drivers/dri/i965/gen8_depth_state.c
View file

@ -250,10 +250,10 @@ pma_fix_enable(const struct brw_context *brw)
*/
const bool hiz_enabled = depth_irb && intel_renderbuffer_has_hiz(depth_irb);
/* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2).
* We always leave this set to EDSC_NORMAL (0).
/* BRW_NEW_FS_PROG_DATA:
* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2).
*/
const bool edsc_not_preps = true;
const bool edsc_not_preps = !brw->wm.prog_data->early_fragment_tests;
/* 3DSTATE_PS_EXTRA::PixelShaderValid is always true. */
const bool pixel_shader_valid = true;

6
src/mesa/drivers/dri/i965/gen8_ps_state.c
View file

@ -119,6 +119,12 @@ upload_wm_state(struct brw_context *brw)
dw1 |= brw->wm.prog_data->barycentric_interp_modes <<
GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
/* BRW_NEW_FS_PROG_DATA */
if (brw->wm.prog_data->early_fragment_tests)
dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
else if (brw->wm.prog_data->base.nr_image_params)
dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_WM << 16 | (2 - 2));
OUT_BATCH(dw1);