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etnaviv: Fix disabling early-z rejection on GC7000L (HALTI5)

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The VIVS_PE_DEPTH_CONFIG_DISABLE_ZS in PE_DEPTH_CONFIG caused depth
write hangs on HALTI5.
This is because the 0x11000000 bits in RA have to be toggled on
when setting this bit to zero. This combination will disable
early-z rejection on GC7000L, which was previously done through
a different bit.
Tested only on GC7000L so far.

Signed-off-by: Lukas F. Hartmann <lukas@mntre.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5456>
This commit is contained in:
Lukas F. Hartmann 2020-06-13 20:55:44 +02:00 • committed by Marge Bot
parent 0d8ae4ac15
commit 785e2707b0
5 changed files with 11 additions and 7 deletions
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3
src/gallium/drivers/etnaviv/etnaviv_context.c
View file

@ -394,9 +394,6 @@ etna_reset_gpu_state(struct etna_context *ctx)
etna_set_state(stream, VIVS_GL_API_MODE, VIVS_GL_API_MODE_OPENGL);
etna_set_state(stream, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x00000001);
/* blob sets this to 0x40000031 on GC7000, seems to make no difference,
* but keep it in mind if depth behaves strangely. */
etna_set_state(stream, VIVS_RA_EARLY_DEPTH, 0x00000031);
etna_set_state(stream, VIVS_PA_W_CLIP_LIMIT, 0x34000001);
etna_set_state(stream, VIVS_PA_FLAGS, 0x00000000); /* blob sets ZCONVERT_BYPASS on GC3000+, this messes up z for us */
etna_set_state(stream, VIVS_PA_VIEWPORT_UNK00A80, 0x38a01404);

1
src/gallium/drivers/etnaviv/etnaviv_emit.c
View file

@ -410,6 +410,7 @@ etna_emit_state(struct etna_context *ctx)
}
if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
/*00E00*/ EMIT_STATE(RA_CONTROL, ctx->shader_state.RA_CONTROL);
/*00E08*/ EMIT_STATE(RA_EARLY_DEPTH, etna_zsa_state(ctx->zsa)->RA_DEPTH_CONFIG);
}
if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
/*01004*/ EMIT_STATE(PS_OUTPUT_REG, ctx->shader_state.PS_OUTPUT_REG);

4
src/gallium/drivers/etnaviv/etnaviv_state.c
View file

@ -250,9 +250,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
depth_format |
COND(depth_supertiled, VIVS_PE_DEPTH_CONFIG_SUPER_TILED) |
VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z |
VIVS_PE_DEPTH_CONFIG_UNK18 | /* something to do with clipping? */
COND(screen->specs.halti >= 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS) /* Needs to be enabled on GC7000, otherwise depth writes hang w/ TS - apparently it does something else now */
;
VIVS_PE_DEPTH_CONFIG_UNK18; /* something to do with clipping? */
/* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
/* merged with depth_stencil_alpha */

9
src/gallium/drivers/etnaviv/etnaviv_zsa.c
View file

@ -110,7 +110,8 @@ etna_zsa_state_create(struct pipe_context *pctx,
COND(so->depth.writemask, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE) |
COND(early_z, VIVS_PE_DEPTH_CONFIG_EARLY_Z) |
/* this bit changed meaning with HALTI5: */
COND(disable_zs && screen->specs.halti < 5, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS);
COND((disable_zs && screen->specs.halti < 5) || ((early_z || disable_zs) && VIV_FEATURE(screen, chipMinorFeatures5, RA_WRITE_DEPTH)), VIVS_PE_DEPTH_CONFIG_DISABLE_ZS);
cs->PE_ALPHA_OP =
COND(so->alpha.enabled, VIVS_PE_ALPHA_OP_ALPHA_TEST) |
VIVS_PE_ALPHA_OP_ALPHA_FUNC(so->alpha.func) |
@ -137,6 +138,12 @@ etna_zsa_state_create(struct pipe_context *pctx,
VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(stencil_back->writemask);
}
/* blob sets this to 0x40000031 on GC7000, seems to make no difference,
* but keep it in mind if depth behaves strangely. */
cs->RA_DEPTH_CONFIG = 0x00000031;
if (VIV_FEATURE(screen, chipMinorFeatures5, RA_WRITE_DEPTH) && !disable_zs && !early_z)
cs->RA_DEPTH_CONFIG |= 0x11000000;
/* XXX does alpha/stencil test affect PE_COLOR_FORMAT_OVERWRITE? */
return cs;
}

1
src/gallium/drivers/etnaviv/etnaviv_zsa.h
View file

@ -39,6 +39,7 @@ struct etna_zsa_state {
uint32_t PE_STENCIL_CONFIG[2];
uint32_t PE_STENCIL_CONFIG_EXT;
uint32_t PE_STENCIL_CONFIG_EXT2[2];
uint32_t RA_DEPTH_CONFIG;
};