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r600,compute: setup compute sampler states and views

Browse source 
v2: Add compute mode flag to sampler state setup (Marek).
    Drop branches which avoid reference counting (Marek).
    Simplify unset branch condition (Marek).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Zoltan Gilian 2015-07-07 23:38:27 +02:00
parent 7f4ad692a1
commit 78493c3318
5 changed files with 54 additions and 40 deletions
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25
src/gallium/drivers/r600/evergreen_compute.c
View file

@ -487,6 +487,12 @@ static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout,
/* Emit constant buffer state */
r600_emit_atom(ctx, &ctx->constbuf_state[PIPE_SHADER_COMPUTE].atom);
/* Emit sampler state */
r600_emit_atom(ctx, &ctx->samplers[PIPE_SHADER_COMPUTE].states.atom);
/* Emit sampler view (texture resource) state */
r600_emit_atom(ctx, &ctx->samplers[PIPE_SHADER_COMPUTE].views.atom);
/* Emit compute shader state */
r600_emit_atom(ctx, &ctx->cs_shader_state.atom);
@ -655,25 +661,6 @@ static void evergreen_set_compute_resources(struct pipe_context * ctx_,
}
}
void evergreen_set_cs_sampler_view(struct pipe_context *ctx_,
unsigned start_slot, unsigned count,
struct pipe_sampler_view **views)
{
struct r600_pipe_sampler_view **resource =
(struct r600_pipe_sampler_view **)views;
for (unsigned i = 0; i < count; i++) {
if (resource[i]) {
assert(i+1 < 12);
/* XXX: Implement */
assert(!"Compute samplers not implemented.");
///FETCH0 = VTX0 (param buffer),
//FETCH1 = VTX1 (global buffer pool), FETCH2... = TEX
}
}
}
static void evergreen_set_global_binding(
struct pipe_context *ctx_, unsigned first, unsigned n,
struct pipe_resource **resources,

46
src/gallium/drivers/r600/evergreen_state.c
View file

@ -1984,7 +1984,7 @@ static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct
static void evergreen_emit_sampler_views(struct r600_context *rctx,
struct r600_samplerview_state *state,
unsigned resource_id_base)
unsigned resource_id_base, unsigned pkt_flags)
{
struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
uint32_t dirty_mask = state->dirty_mask;
@ -1997,7 +1997,7 @@ static void evergreen_emit_sampler_views(struct r600_context *rctx,
rview = state->views[resource_index];
assert(rview);
radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
radeon_emit(cs, (resource_id_base + resource_index) * 8);
radeon_emit_array(cs, rview->tex_resource_words, 8);
@ -2006,11 +2006,11 @@ static void evergreen_emit_sampler_views(struct r600_context *rctx,
rview->tex_resource->b.b.nr_samples > 1 ?
RADEON_PRIO_SHADER_TEXTURE_MSAA :
RADEON_PRIO_SHADER_TEXTURE_RO);
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
radeon_emit(cs, reloc);
if (!rview->skip_mip_address_reloc) {
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
radeon_emit(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
radeon_emit(cs, reloc);
}
}
@ -2019,23 +2019,33 @@ static void evergreen_emit_sampler_views(struct r600_context *rctx,
static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
{
evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, 176 + R600_MAX_CONST_BUFFERS);
evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
176 + R600_MAX_CONST_BUFFERS, 0);
}
static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
{
evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, 336 + R600_MAX_CONST_BUFFERS);
evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
336 + R600_MAX_CONST_BUFFERS, 0);
}
static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
{
evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_MAX_CONST_BUFFERS);
evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
R600_MAX_CONST_BUFFERS, 0);
}
static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
{
evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
816 + 2, RADEON_CP_PACKET3_COMPUTE_MODE);
}
static void evergreen_emit_sampler_states(struct r600_context *rctx,
struct r600_textures_info *texinfo,
unsigned resource_id_base,
unsigned border_index_reg)
unsigned border_index_reg,
unsigned pkt_flags)
{
struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
uint32_t dirty_mask = texinfo->states.dirty_mask;
@ -2047,7 +2057,7 @@ static void evergreen_emit_sampler_states(struct r600_context *rctx,
rstate = texinfo->states.states[i];
assert(rstate);
radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
radeon_emit(cs, PKT3(PKT3_SET_SAMPLER, 3, 0) | pkt_flags);
radeon_emit(cs, (resource_id_base + i) * 3);
radeon_emit_array(cs, rstate->tex_sampler_words, 3);
@ -2062,17 +2072,27 @@ static void evergreen_emit_sampler_states(struct r600_context *rctx,
static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
{
evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0);
}
static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
{
evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A428_TD_GS_SAMPLER0_BORDER_INDEX);
evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0);
}
static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
{
evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0);
}
static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
{
evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
R_00A464_TD_CS_SAMPLER0_BORDER_INDEX,
RADEON_CP_PACKET3_COMPUTE_MODE);
}
static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
@ -3435,12 +3455,14 @@ void evergreen_init_state_functions(struct r600_context *rctx)
r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
/* resources */
r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);

5
src/gallium/drivers/r600/evergreend.h
View file

@ -1253,6 +1253,11 @@
#define R_00A430_TD_GS_SAMPLER0_BORDER_GREEN 0x00A430
#define R_00A434_TD_GS_SAMPLER0_BORDER_BLUE 0x00A434
#define R_00A438_TD_GS_SAMPLER0_BORDER_ALPHA 0x00A438
#define R_00A464_TD_CS_SAMPLER0_BORDER_INDEX 0x00A464
#define R_00A468_TD_CS_SAMPLER0_BORDER_RED 0x00A468
#define R_00A46C_TD_CS_SAMPLER0_BORDER_GREEN 0x00A46C
#define R_00A470_TD_CS_SAMPLER0_BORDER_BLUE 0x00A470
#define R_00A474_TD_CS_SAMPLER0_BORDER_ALPHA 0x00A474
#define R_03C000_SQ_TEX_SAMPLER_WORD0_0 0x03C000
#define S_03C000_CLAMP_X(x) (((x) & 0x7) << 0)

7
src/gallium/drivers/r600/r600_pipe.h
View file

@ -36,7 +36,7 @@
#include "util/list.h"
#include "util/u_transfer.h"
#define R600_NUM_ATOMS 73
#define R600_NUM_ATOMS 75
#define R600_MAX_VIEWPORTS 16
@ -589,11 +589,6 @@ void compute_memory_pool_delete(struct compute_memory_pool* pool);
struct compute_memory_pool* compute_memory_pool_new(
struct r600_screen *rscreen);
/* evergreen_compute.c */
void evergreen_set_cs_sampler_view(struct pipe_context *ctx_,
unsigned start_slot, unsigned count,
struct pipe_sampler_view **views);
/* evergreen_state.c */
struct pipe_sampler_view *
evergreen_create_sampler_view_custom(struct pipe_context *ctx,

11
src/gallium/drivers/r600/r600_state_common.c
View file

@ -407,6 +407,11 @@ static void r600_bind_sampler_states(struct pipe_context *pipe,
assert(start == 0); /* XXX fix below */
if (!states) {
disable_mask = ~0u;
count = 0;
}
for (i = 0; i < count; i++) {
struct r600_pipe_sampler_state *rstate = rstates[i];
@ -596,9 +601,9 @@ static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
assert(start == 0); /* XXX fix below */
if (shader == PIPE_SHADER_COMPUTE) {
evergreen_set_cs_sampler_view(pipe, start, count, views);
return;
if (!views) {
disable_mask = ~0u;
count = 0;
}
remaining_mask = dst->views.enabled_mask & disable_mask;