From 77e5f149ebb924775d6b53d03353d0df13870f51 Mon Sep 17 00:00:00 2001 From: Joshua Ashton Date: Sun, 26 Sep 2021 19:01:20 +0100 Subject: [PATCH] ac/surface: Expose modifiers capable of DCC image stores first MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These also have a higher compressed block size. Signed-off-by: Joshua Ashton Reviewed-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák Part-of: --- src/amd/common/ac_surface.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index bbcef821e62..30894648fdd 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -353,6 +353,19 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)) + if (info->chip_class >= GFX10_3) { + if (info->max_render_backends == 1) { + ADD_MOD(AMD_FMT_MOD | common_dcc | + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)) + } + + ADD_MOD(AMD_FMT_MOD | common_dcc | + AMD_FMT_MOD_SET(DCC_RETILE, 1) | + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)) + } + if (info->family == CHIP_NAVI12 || info->family == CHIP_NAVI14 || info->chip_class >= GFX10_3) { bool independent_128b = info->chip_class >= GFX10_3; @@ -361,12 +374,6 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, independent_128b) | AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)) - - if (info->chip_class >= GFX10_3) { - ADD_MOD(AMD_FMT_MOD | common_dcc | - AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | - AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)) - } } ADD_MOD(AMD_FMT_MOD | common_dcc | @@ -374,13 +381,6 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, independent_128b) | AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B)) - - if (info->chip_class >= GFX10_3) { - ADD_MOD(AMD_FMT_MOD | common_dcc | - AMD_FMT_MOD_SET(DCC_RETILE, 1) | - AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | - AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B)) - } } ADD_MOD(AMD_FMT_MOD |