fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-02 05:48:07 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

r600: clean up initial shader register setup

Browse source 
This is taken from Glenn Kennards scratch series, but separated
out as a cleanup by me.

Reviewed-By: Gert Wollny <gw.fossdev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Glenn Kennard 2018-02-07 06:24:07 +10:00 • committed by Dave Airlie
parent b936f4d1ca
commit 77b1b33724
1 changed files with 17 additions and 20 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

37
src/gallium/drivers/r600/r600_shader.c
View file

@ -3344,41 +3344,38 @@ static int r600_shader_from_tgsi(struct r600_context *rctx,
ctx.file_offset[TGSI_FILE_CONSTANT] = 512;
ctx.file_offset[TGSI_FILE_IMMEDIATE] = V_SQ_ALU_SRC_LITERAL;
ctx.bc->ar_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
ctx.info.file_max[TGSI_FILE_TEMPORARY] + 1;
ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1;
ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2;
int regno = ctx.file_offset[TGSI_FILE_TEMPORARY] +
ctx.info.file_max[TGSI_FILE_TEMPORARY];
ctx.bc->ar_reg = ++regno;
ctx.bc->index_reg[0] = ++regno;
ctx.bc->index_reg[1] = ++regno;
if (ctx.type == PIPE_SHADER_TESS_CTRL) {
ctx.tess_input_info = ctx.bc->ar_reg + 3;
ctx.tess_output_info = ctx.bc->ar_reg + 4;
ctx.temp_reg = ctx.bc->ar_reg + 5;
ctx.tess_input_info = ++regno;
ctx.tess_output_info = ++regno;
} else if (ctx.type == PIPE_SHADER_TESS_EVAL) {
ctx.tess_input_info = 0;
ctx.tess_output_info = ctx.bc->ar_reg + 3;
ctx.temp_reg = ctx.bc->ar_reg + 4;
ctx.tess_output_info = ++regno;
} else if (ctx.type == PIPE_SHADER_GEOMETRY) {
ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3;
ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4;
ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5;
ctx.gs_export_gpr_tregs[3] = ctx.bc->ar_reg + 6;
ctx.temp_reg = ctx.bc->ar_reg + 7;
ctx.gs_export_gpr_tregs[0] = ++regno;
ctx.gs_export_gpr_tregs[1] = ++regno;
ctx.gs_export_gpr_tregs[2] = ++regno;
ctx.gs_export_gpr_tregs[3] = ++regno;
if (ctx.shader->gs_tri_strip_adj_fix) {
ctx.gs_rotated_input[0] = ctx.bc->ar_reg + 7;
ctx.gs_rotated_input[1] = ctx.bc->ar_reg + 8;
ctx.temp_reg += 2;
ctx.gs_rotated_input[0] = ++regno;
ctx.gs_rotated_input[1] = ++regno;
} else {
ctx.gs_rotated_input[0] = 0;
ctx.gs_rotated_input[1] = 1;
}
} else {
ctx.temp_reg = ctx.bc->ar_reg + 3;
}
if (shader->uses_images) {
ctx.thread_id_gpr = ctx.temp_reg++;
ctx.thread_id_gpr = ++regno;
ctx.thread_id_gpr_loaded = false;
}
ctx.temp_reg = ++regno;
shader->max_arrays = 0;
shader->num_arrays = 0;