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nvc0/ir: add hazard for 2nd dim of vfetch/load indirect argument

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Apparently a multi-word load can potentially overwrite the indirect
sources, so make sure that RA picks different registers for those.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Ilia Mirkin 2015-07-23 02:27:04 -04:00
parent 7cf2bffe82
commit 77672cdb64
1 changed files with 2 additions and 0 deletions
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2
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
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@ -2066,6 +2066,8 @@ RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb)
condenseDefs(i);
if (i->src(0).isIndirect(0) && typeSizeof(i->dType) >= 8)
addHazard(i, i->src(0).getIndirect(0));
if (i->src(0).isIndirect(1) && typeSizeof(i->dType) >= 8)
addHazard(i, i->src(0).getIndirect(1));
} else
if (i->op == OP_UNION ||
i->op == OP_MERGE ||