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i915g: fix transfer coherency

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The kernel drm takes care of all coherency as long as we don't forget
to submit all outstanding commands in the batchbuffer ...

Also move batchbuffer initialization up because otherwise transfers
for some helper textures fail with a segmentation fault.

And kill the dead code, flushes should now be correct everywhere.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2011-03-12 22:57:17 +01:00
parent f608795588
commit 7735f8c6e5
3 changed files with 7 additions and 26 deletions
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8
src/gallium/drivers/i915/i915_context.c
View file

@ -151,6 +151,10 @@ i915_create_context(struct pipe_screen *screen, void *priv)
util_slab_create(&i915->transfer_pool, sizeof(struct pipe_transfer),
16, UTIL_SLAB_SINGLETHREADED);
/* Batch stream debugging is a bit hacked up at the moment:
*/
i915->batch = i915->iws->batchbuffer_create(i915->iws);
/*
* Create drawing context and plug our rendering stage into it.
*/
@ -183,9 +187,5 @@ i915_create_context(struct pipe_screen *screen, void *priv)
i915->dynamic_dirty = ~0;
i915->flush_dirty = 0;
/* Batch stream debugging is a bit hacked up at the moment:
*/
i915->batch = i915->iws->batchbuffer_create(i915->iws);
return &i915->base;
}

22
src/gallium/drivers/i915/i915_flush.c
View file

@ -45,28 +45,6 @@ static void i915_flush_pipe( struct pipe_context *pipe,
draw_flush(i915->draw);
#if 0
/* Do we need to emit an MI_FLUSH command to flush the hardware
* caches?
*/
/* XXX These flags are now implicit. All of them. */
if (flags & (PIPE_FLUSH_RENDER_CACHE | PIPE_FLUSH_TEXTURE_CACHE)) {
unsigned flush = MI_FLUSH;
if (!(flags & PIPE_FLUSH_RENDER_CACHE))
flush |= INHIBIT_FLUSH_RENDER_CACHE;
if (flags & PIPE_FLUSH_TEXTURE_CACHE)
flush |= FLUSH_MAP_CACHE;
if (!BEGIN_BATCH(1)) {
FLUSH_BATCH(NULL);
assert(BEGIN_BATCH(1));
}
OUT_BATCH( flush );
}
#endif
if (i915->batch->map == i915->batch->ptr) {
return;
}

3
src/gallium/drivers/i915/i915_resource_texture.c
View file

@ -759,6 +759,9 @@ i915_texture_transfer_map(struct pipe_context *pipe,
assert(box->z == 0);
offset = i915_texture_offset(tex, transfer->level, box->z);
/* TODO this is a sledgehammer */
pipe->flush(pipe, NULL);
map = iws->buffer_map(iws, tex->buffer,
(transfer->usage & PIPE_TRANSFER_WRITE) ? TRUE : FALSE);
if (map == NULL)