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ntt: switch to derivative intrinsics

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30572>
This commit is contained in:
Alyssa Rosenzweig 2024-07-23 17:13:56 -04:00 • committed by Marge Bot
parent 9966365fe0
commit 772e6d61b9
5 changed files with 22 additions and 7 deletions
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22
src/gallium/auxiliary/nir/nir_to_tgsi.c
View file

@ -1519,12 +1519,6 @@ ntt_emit_alu(struct ntt_compile *c, nir_alu_instr *instr)
[nir_op_fsign] = { TGSI_OPCODE_SSG, TGSI_OPCODE_DSSG },
[nir_op_isign] = { TGSI_OPCODE_ISSG, TGSI_OPCODE_I64SSG },
[nir_op_ftrunc] = { TGSI_OPCODE_TRUNC, TGSI_OPCODE_DTRUNC },
[nir_op_fddx] = { TGSI_OPCODE_DDX },
[nir_op_fddy] = { TGSI_OPCODE_DDY },
[nir_op_fddx_coarse] = { TGSI_OPCODE_DDX },
[nir_op_fddy_coarse] = { TGSI_OPCODE_DDY },
[nir_op_fddx_fine] = { TGSI_OPCODE_DDX_FINE },
[nir_op_fddy_fine] = { TGSI_OPCODE_DDY_FINE },
[nir_op_pack_half_2x16] = { TGSI_OPCODE_PK2H },
[nir_op_unpack_half_2x16] = { TGSI_OPCODE_UP2H },
[nir_op_ibitfield_extract] = { TGSI_OPCODE_IBFE },
@ -2599,6 +2593,21 @@ ntt_emit_intrinsic(struct ntt_compile *c, nir_intrinsic_instr *instr)
ntt_READ_INVOC(c, ntt_get_dest(c, &instr->def), ntt_get_src(c, instr->src[0]), ntt_get_src(c, instr->src[1]));
return;
case nir_intrinsic_ddx:
case nir_intrinsic_ddx_coarse:
ntt_DDX(c, ntt_get_dest(c, &instr->def), ntt_get_src(c, instr->src[0]));
return;
case nir_intrinsic_ddx_fine:
ntt_DDX_FINE(c, ntt_get_dest(c, &instr->def), ntt_get_src(c, instr->src[0]));
return;
case nir_intrinsic_ddy:
case nir_intrinsic_ddy_coarse:
ntt_DDY(c, ntt_get_dest(c, &instr->def), ntt_get_src(c, instr->src[0]));
return;
case nir_intrinsic_ddy_fine:
ntt_DDY_FINE(c, ntt_get_dest(c, &instr->def), ntt_get_src(c, instr->src[0]));
return;
case nir_intrinsic_load_ssbo:
case nir_intrinsic_store_ssbo:
case nir_intrinsic_ssbo_atomic:
@ -4076,6 +4085,7 @@ static const nir_shader_compiler_options nir_to_tgsi_compiler_options = {
* workgroup id.
*/
.lower_cs_local_index_to_id = true,
.has_ddx_intrinsics = true,
};
/* Returns a default compiler options for drivers with only nir-to-tgsi-based

2
src/gallium/drivers/i915/i915_screen.c
View file

@ -126,6 +126,7 @@ static const nir_shader_compiler_options i915_compiler_options = {
.max_unroll_iterations = 32,
.no_integers = true,
.has_fused_comp_and_csel = true,
.has_ddx_intrinsics = true,
};
static const struct nir_shader_compiler_options gallivm_nir_options = {
@ -171,6 +172,7 @@ static const struct nir_shader_compiler_options gallivm_nir_options = {
.lower_vector_cmp = true,
.lower_device_index_to_zero = true,
/* .support_16bit_alu = true, */
.has_ddx_intrinsics = true,
};
static const void *

1
src/gallium/drivers/nouveau/nv30/nv30_screen.c
View file

@ -483,6 +483,7 @@ static const nir_shader_compiler_options nv30_base_compiler_options = {
.no_integers = true,
.use_interpolated_input_intrinsics = true,
.has_ddx_intrinsics = true,
};
static const void *

1
src/gallium/drivers/softpipe/sp_screen.c
View file

@ -95,6 +95,7 @@ static const nir_shader_compiler_options sp_compiler_options = {
* workgroup id.
*/
.lower_cs_local_index_to_id = true,
.has_ddx_intrinsics = true,
};
static const void *

3
src/gallium/drivers/svga/svga_screen.c
View file

@ -723,7 +723,8 @@ vgpu10_get_shader_param(struct pipe_screen *screen,
.lower_vector_cmp = true, \
.lower_cs_local_index_to_id = true, \
.max_unroll_iterations = 32, \
.use_interpolated_input_intrinsics = true
.use_interpolated_input_intrinsics = true, \
.has_ddx_intrinsics = true
#define VGPU10_OPTIONS \
.lower_doubles_options = nir_lower_dfloor | nir_lower_dsign | nir_lower_dceil | nir_lower_dtrunc | nir_lower_dround_even, \