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intel/eu/xe2+: Fix src1 length bits of SEND instruction with UGM target.

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Rework:
 * Francisco Jerez: Specify the src1 length value in the correct
   units. Don't break earlier platforms.

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28283>
This commit is contained in:
Rohan Garg 2022-09-12 17:00:32 -07:00 • committed by Marge Bot
parent fb6638da80
commit 7668de019b
1 changed files with 5 additions and 0 deletions
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5
src/intel/compiler/brw_eu_emit.c
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@ -1598,6 +1598,11 @@ brw_send_indirect_split_message(struct brw_codegen *p,
assert((ex_desc.subnr & 0x3) == 0);
brw_inst_set_send_sel_reg32_ex_desc(devinfo, send, 1);
brw_inst_set_send_ex_desc_ia_subreg_nr(devinfo, send, phys_subnr(devinfo, ex_desc) >> 2);
if (devinfo->ver >= 20 && sfid == GFX12_SFID_UGM) {
const unsigned ex_mlen = brw_message_ex_desc_ex_mlen(devinfo, ex_desc_imm);
brw_inst_set_bits(send, 103, 99, ex_mlen / reg_unit(devinfo));
}
}
if (ex_bso) {