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radeonsi: move CB_TARGET_MASK into fb/blend state

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Signed-off-by: Christian König <deathsimple@vodafone.de>
This commit is contained in:
Christian König 2012-07-18 11:36:28 +02:00
parent e6937211da
commit 76660dfcce
4 changed files with 23 additions and 12 deletions
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1
src/gallium/drivers/radeonsi/evergreen_hw_context.c
View file

@ -51,7 +51,6 @@ static const struct r600_reg si_context_reg_list[] = {
{R_028080_TA_BC_BASE_ADDR, REG_FLAG_NEED_BO},
{GROUP_FORCE_NEW_BLOCK, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0},
{R_028238_CB_TARGET_MASK, 0},
{GROUP_FORCE_NEW_BLOCK, 0},
{R_028400_VGT_MAX_VTX_INDX, 0},
{R_028404_VGT_MIN_VTX_INDX, 0},

12
src/gallium/drivers/radeonsi/r600_state_common.c
View file

@ -554,10 +554,9 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
struct pipe_draw_info info = *dinfo;
struct r600_draw rdraw = {};
struct pipe_index_buffer ib = {};
unsigned prim, mask, ls_mask = 0;
unsigned prim, ls_mask = 0;
struct r600_block *dirty_block = NULL, *next_block = NULL;
struct r600_atom *state = NULL, *next_state = NULL;
struct si_state_blend *blend;
int i;
if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
@ -569,11 +568,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
if (!rctx->ps_shader || !rctx->vs_shader)
return;
/* only temporary */
if (!rctx->queued.named.blend)
return;
blend = rctx->queued.named.blend;
si_update_derived_state(rctx);
r600_vertex_buffer_update(rctx);
@ -617,13 +611,10 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
rctx->vs_shader_so_strides = rctx->vs_shader->so_strides;
mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
rctx->vgt.id = R600_PIPE_STATE_VGT;
rctx->vgt.nregs = 0;
r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, blend->cb_target_mask & mask, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
@ -641,7 +632,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
rctx->vgt.nregs = 0;
r600_pipe_state_mod_reg(&rctx->vgt, prim);
r600_pipe_state_mod_reg(&rctx->vgt, blend->cb_target_mask & mask);
r600_pipe_state_mod_reg(&rctx->vgt, ~0);
r600_pipe_state_mod_reg(&rctx->vgt, 0);
r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);

21
src/gallium/drivers/radeonsi/si_state.c
View file

@ -30,6 +30,25 @@
#include "si_state.h"
#include "sid.h"
/*
* inferred framebuffer and blender state
*/
static void si_update_fb_blend_state(struct r600_context *rctx)
{
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct si_state_blend *blend = rctx->queued.named.blend;
uint32_t mask;
if (pm4 == NULL || blend == NULL)
return;
mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
mask &= blend->cb_target_mask;
si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
si_pm4_set_state(rctx, fb_blend, pm4);
}
/*
* Blender functions
*/
@ -169,6 +188,7 @@ static void si_bind_blend_state(struct pipe_context *ctx, void *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
si_update_fb_blend_state(rctx);
}
static void si_delete_blend_state(struct pipe_context *ctx, void *state)
@ -1267,6 +1287,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
si_pm4_set_state(rctx, framebuffer, pm4);
si_update_fb_rs_state(rctx);
si_update_fb_blend_state(rctx);
}
void si_init_state_functions(struct r600_context *rctx)

1
src/gallium/drivers/radeonsi/si_state.h
View file

@ -72,6 +72,7 @@ union si_state {
struct si_state_rasterizer *rasterizer;
struct si_state_dsa *dsa;
struct si_pm4_state *fb_rs;
struct si_pm4_state *fb_blend;
struct si_pm4_state *dsa_stencil_ref;
} named;
struct si_pm4_state *array[0];