mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-06 09:28:07 +02:00
i965: Move the rest of intel_tex_layout.c into brw_tex_layout.c.
The texture alignment unit functions are called from brw_tex_layout.c, so it makes sense to put them there. Since the only caller of intel_get_texture_alignment_unit() is in brw_tex_layout.c, it could be made into a static function. However, this patch instead simply folds it into the caller, as it's only two lines anyway. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
This commit is contained in:
Kenneth Graunke
parent
466aa712b6
commit
764afc48cf
6 changed files with 102 additions and 191 deletions
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@ -24,7 +24,6 @@ i965_FILES = \
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intel_tex.c \
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intel_tex_copy.c \
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intel_tex_image.c \
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intel_tex_layout.c \
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intel_tex_subimage.c \
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intel_tex_validate.c \
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brw_blorp.cpp \
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@ -33,12 +33,111 @@
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*/
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#include "intel_mipmap_tree.h"
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#include "intel_tex_layout.h"
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#include "intel_context.h"
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#include "main/macros.h"
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#define FILE_DEBUG_FLAG DEBUG_MIPTREE
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static unsigned int
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intel_horizontal_texture_alignment_unit(struct intel_context *intel,
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gl_format format)
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{
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/**
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* From the "Alignment Unit Size" section of various specs, namely:
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* - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
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* - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
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* - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
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* - BSpec (for Ivybridge and slight variations in separate stencil)
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*
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* +----------------------------------------------------------------------+
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* | | alignment unit width ("i") |
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* | Surface Property |-----------------------------|
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* | | 915 | 965 | ILK | SNB | IVB |
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* +----------------------------------------------------------------------+
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* | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
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* | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
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* | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
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* | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
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* | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
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* | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
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* | All Others | 4 | 4 | 4 | 4 | 4 |
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* +----------------------------------------------------------------------+
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*
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* On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
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* "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
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*/
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if (_mesa_is_format_compressed(format)) {
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/* The hardware alignment requirements for compressed textures
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* happen to match the block boundaries.
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*/
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unsigned int i, j;
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_mesa_get_format_block_size(format, &i, &j);
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return i;
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}
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if (format == MESA_FORMAT_S8)
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return 8;
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/* The depth alignment requirements in the table above are for rendering to
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* depth miplevels using the LOD control fields. We don't use LOD control
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* fields, and instead use page offsets plus intra-tile x/y offsets, which
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* require that the low 3 bits are zero. To reduce the number of x/y
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* offset workaround blits we do, align the X to 8, which depth texturing
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* can handle (sadly, it can't handle 8 in the Y direction).
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*/
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if (intel->gen >= 7 &&
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_mesa_get_format_base_format(format) == GL_DEPTH_COMPONENT)
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return 8;
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return 4;
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}
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static unsigned int
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intel_vertical_texture_alignment_unit(struct intel_context *intel,
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gl_format format)
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{
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/**
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* From the "Alignment Unit Size" section of various specs, namely:
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* - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
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* - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
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* - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
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* - BSpec (for Ivybridge and slight variations in separate stencil)
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*
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* +----------------------------------------------------------------------+
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* | | alignment unit height ("j") |
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* | Surface Property |-----------------------------|
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* | | 915 | 965 | ILK | SNB | IVB |
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* +----------------------------------------------------------------------+
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* | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
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* | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
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* | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
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* | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
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* | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 |
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* | All Others | 2 | 2 | 2 | 2 | 2 |
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* +----------------------------------------------------------------------+
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*
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* On SNB+, non-special cases can be overridden by setting the SURFACE_STATE
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* "Surface Vertical Alignment" field to VALIGN_2 or VALIGN_4.
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*
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* We currently don't support multisampling.
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*/
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if (_mesa_is_format_compressed(format))
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return 4;
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if (format == MESA_FORMAT_S8)
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return intel->gen >= 7 ? 8 : 4;
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GLenum base_format = _mesa_get_format_base_format(format);
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if (intel->gen >= 6 &&
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(base_format == GL_DEPTH_COMPONENT ||
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base_format == GL_DEPTH_STENCIL)) {
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return 4;
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}
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return 2;
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}
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static void
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brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
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{
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@ -212,8 +311,8 @@ brw_miptree_layout_texture_3d(struct intel_context *intel,
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void
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brw_miptree_layout(struct intel_context *intel, struct intel_mipmap_tree *mt)
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{
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intel_get_texture_alignment_unit(intel, mt->format,
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&mt->align_w, &mt->align_h);
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mt->align_w = intel_horizontal_texture_alignment_unit(intel, mt->format);
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mt->align_h = intel_vertical_texture_alignment_unit(intel, mt->format);
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switch (mt->target) {
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case GL_TEXTURE_CUBE_MAP:
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@ -34,7 +34,6 @@
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#include "intel_mipmap_tree.h"
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#include "intel_regions.h"
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#include "intel_resolve_map.h"
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#include "intel_tex_layout.h"
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#include "intel_tex.h"
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#include "intel_blit.h"
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@ -1,147 +0,0 @@
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/**************************************************************************
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*
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* Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keith@tungstengraphics.com>
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* Michel Dänzer <michel@tungstengraphics.com>
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*/
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#include "intel_mipmap_tree.h"
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#include "intel_tex_layout.h"
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#include "intel_context.h"
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#include "main/image.h"
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#include "main/macros.h"
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static unsigned int
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intel_horizontal_texture_alignment_unit(struct intel_context *intel,
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gl_format format)
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{
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/**
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* From the "Alignment Unit Size" section of various specs, namely:
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* - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
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* - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
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* - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
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* - BSpec (for Ivybridge and slight variations in separate stencil)
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*
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* +----------------------------------------------------------------------+
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* | | alignment unit width ("i") |
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* | Surface Property |-----------------------------|
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* | | 915 | 965 | ILK | SNB | IVB |
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* +----------------------------------------------------------------------+
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* | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
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* | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
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* | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
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* | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
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* | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
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* | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
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* | All Others | 4 | 4 | 4 | 4 | 4 |
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* +----------------------------------------------------------------------+
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*
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* On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
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* "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
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*/
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if (_mesa_is_format_compressed(format)) {
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/* The hardware alignment requirements for compressed textures
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* happen to match the block boundaries.
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*/
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unsigned int i, j;
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_mesa_get_format_block_size(format, &i, &j);
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return i;
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}
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if (format == MESA_FORMAT_S8)
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return 8;
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/* The depth alignment requirements in the table above are for rendering to
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* depth miplevels using the LOD control fields. We don't use LOD control
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* fields, and instead use page offsets plus intra-tile x/y offsets, which
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* require that the low 3 bits are zero. To reduce the number of x/y
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* offset workaround blits we do, align the X to 8, which depth texturing
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* can handle (sadly, it can't handle 8 in the Y direction).
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*/
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if (intel->gen >= 7 &&
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_mesa_get_format_base_format(format) == GL_DEPTH_COMPONENT)
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return 8;
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return 4;
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}
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static unsigned int
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intel_vertical_texture_alignment_unit(struct intel_context *intel,
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gl_format format)
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{
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/**
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* From the "Alignment Unit Size" section of various specs, namely:
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* - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
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* - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
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* - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
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* - BSpec (for Ivybridge and slight variations in separate stencil)
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*
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* +----------------------------------------------------------------------+
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* | | alignment unit height ("j") |
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* | Surface Property |-----------------------------|
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* | | 915 | 965 | ILK | SNB | IVB |
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* +----------------------------------------------------------------------+
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* | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
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* | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
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* | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
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* | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
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* | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 |
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* | All Others | 2 | 2 | 2 | 2 | 2 |
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* +----------------------------------------------------------------------+
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*
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* On SNB+, non-special cases can be overridden by setting the SURFACE_STATE
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* "Surface Vertical Alignment" field to VALIGN_2 or VALIGN_4.
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*
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* We currently don't support multisampling.
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*/
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if (_mesa_is_format_compressed(format))
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return 4;
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if (format == MESA_FORMAT_S8)
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return intel->gen >= 7 ? 8 : 4;
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GLenum base_format = _mesa_get_format_base_format(format);
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if (intel->gen >= 6 &&
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(base_format == GL_DEPTH_COMPONENT ||
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base_format == GL_DEPTH_STENCIL)) {
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return 4;
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}
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return 2;
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}
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void
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intel_get_texture_alignment_unit(struct intel_context *intel,
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gl_format format,
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unsigned int *w, unsigned int *h)
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{
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*w = intel_horizontal_texture_alignment_unit(intel, format);
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*h = intel_vertical_texture_alignment_unit(intel, format);
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}
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@ -1,38 +0,0 @@
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/**************************************************************************
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*
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* Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
|
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* distribute, sub license, and/or sell copies of the Software, and to
|
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* permit persons to whom the Software is furnished to do so, subject to
|
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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||||
* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
|
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
|
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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**************************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keith@tungstengraphics.com>
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* Michel Dänzer <michel@tungstengraphics.com>
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*/
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#include "main/macros.h"
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void
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intel_get_texture_alignment_unit(struct intel_context *intel,
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gl_format format,
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unsigned int *w, unsigned int *h);
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@ -7,7 +7,6 @@
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#include "intel_mipmap_tree.h"
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#include "intel_blit.h"
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#include "intel_tex.h"
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#include "intel_tex_layout.h"
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#define FILE_DEBUG_FLAG DEBUG_TEXTURE
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