fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-09 04:38:03 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

pan/midgard: Extend swizzle packing for vec4/16-bit

Browse source 
We would like to pack not just xyzw swizzles but also efgh swizzles.
This should work for vec4/16-bit. More work will be needed to pack
swizzles for vec8/16-bit and even more work for 8-bit, of course.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
This commit is contained in:
Alyssa Rosenzweig 2019-10-31 14:56:45 -04:00
parent bf5508f7b9
commit 762623381d
1 changed files with 24 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

27
src/panfrost/midgard/midgard_emit.c
View file

@ -136,17 +136,38 @@ mir_pack_swizzle_alu(midgard_instruction *ins)
for (unsigned i = 0; i < 2; ++i) {
unsigned packed = 0;
/* TODO: non-32-bit, non-vec4 */
/* For 32-bit, swizzle packing is stupid-simple. For 16-bit,
* the strategy is to check whether the nibble we're on is
* upper or lower. We need all components to be on the same
* "side"; that much is enforced by the ISA and should have
* been lowered. TODO: 8-bit/64-bit packing. TODO: vec8 */
unsigned first = ins->mask ? ffs(ins->mask) - 1 : 0;
bool upper = ins->swizzle[i][first] > 3;
if (upper && ins->mask)
assert(mir_srcsize(ins, i) <= midgard_reg_mode_16);
for (unsigned c = 0; c < 4; ++c) {
unsigned v = ins->swizzle[i][c];
/* Check vec4 */
assert(v <= 3);
bool t_upper = v > 3;
/* Ensure we're doing something sane */
if (ins->mask & (1 << c)) {
assert(t_upper == upper);
assert(v <= 7);
}
/* Use the non upper part */
v &= 0x3;
packed |= v << (2 * c);
}
src[i].swizzle = packed;
src[i].rep_high = upper;
}
ins->alu.src1 = vector_alu_srco_unsigned(src[0]);