diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 035d9abf90a..c2b9d81f970 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -2255,7 +2255,9 @@ static void si_emit_graphics_shader_pointers(struct si_context *sctx, unsigned i
       if (sctx->gs_attribute_ring_pointer_dirty) {
          gfx12_push_gfx_sh_reg(R_00B230_SPI_SHADER_USER_DATA_GS_0 +
                                GFX9_SGPR_ATTRIBUTE_RING_ADDR * 4,
-                               sctx->screen->attribute_pos_prim_ring->gpu_address);
+                               sctx->ws->cs_is_secure(&sctx->gfx_cs) ?
+                                 sctx->screen->attribute_pos_prim_ring_tmz->gpu_address:
+                                 sctx->screen->attribute_pos_prim_ring->gpu_address);
          sctx->gs_attribute_ring_pointer_dirty = false;
       }
 
@@ -2283,7 +2285,9 @@ static void si_emit_graphics_shader_pointers(struct si_context *sctx, unsigned i
       if (sctx->gs_attribute_ring_pointer_dirty) {
          gfx11_push_gfx_sh_reg(R_00B230_SPI_SHADER_USER_DATA_GS_0 +
                                GFX9_SGPR_ATTRIBUTE_RING_ADDR * 4,
-                               sctx->screen->attribute_pos_prim_ring->gpu_address);
+                               sctx->ws->cs_is_secure(&sctx->gfx_cs) ?
+                                 sctx->screen->attribute_pos_prim_ring_tmz->gpu_address:
+                                 sctx->screen->attribute_pos_prim_ring->gpu_address);
          sctx->gs_attribute_ring_pointer_dirty = false;
       }
 
@@ -2313,7 +2317,9 @@ static void si_emit_graphics_shader_pointers(struct si_context *sctx, unsigned i
          assert(sctx->gfx_level >= GFX11);
          radeon_set_sh_reg(R_00B230_SPI_SHADER_USER_DATA_GS_0 +
                            GFX9_SGPR_ATTRIBUTE_RING_ADDR * 4,
-                           sctx->screen->attribute_pos_prim_ring->gpu_address);
+                           sctx->ws->cs_is_secure(&sctx->gfx_cs) ?
+                              sctx->screen->attribute_pos_prim_ring_tmz->gpu_address:
+                              sctx->screen->attribute_pos_prim_ring->gpu_address);
          sctx->gs_attribute_ring_pointer_dirty = false;
       }
       radeon_end();
diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 8b8be331ab5..572bb1d0771 100644
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -442,6 +442,19 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
    if (unlikely(radeon_uses_secure_bos(ctx->ws))) {
       is_secure = ctx->ws->cs_is_secure(&ctx->gfx_cs);
 
+      if (is_secure && !ctx->screen->attribute_pos_prim_ring_tmz) {
+         ctx->screen->attribute_pos_prim_ring_tmz =
+            si_aligned_buffer_create(&ctx->screen->b,
+                                     PIPE_RESOURCE_FLAG_UNMAPPABLE |
+                                     SI_RESOURCE_FLAG_32BIT |
+                                     SI_RESOURCE_FLAG_DRIVER_INTERNAL |
+                                     PIPE_RESOURCE_FLAG_ENCRYPTED |
+                                     SI_RESOURCE_FLAG_DISCARDABLE,
+                                     PIPE_USAGE_DEFAULT,
+                                     ctx->screen->info.total_attribute_pos_prim_ring_size,
+                                     2 * 1024 * 1024);
+      }
+
       si_install_draw_wrapper(ctx, si_draw_vbo_tmz_preamble,
                               si_draw_vstate_tmz_preamble);
    }
@@ -487,10 +500,14 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
    si_mark_atom_dirty(ctx, &ctx->atoms.s.barrier);
    si_mark_atom_dirty(ctx, &ctx->atoms.s.spi_ge_ring_state);
 
-   if (ctx->screen->attribute_pos_prim_ring) {
+   if (ctx->screen->attribute_pos_prim_ring && !is_secure) {
       radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->screen->attribute_pos_prim_ring,
                                 RADEON_USAGE_READWRITE | RADEON_PRIO_SHADER_RINGS);
    }
+   if (ctx->screen->attribute_pos_prim_ring_tmz && is_secure) {
+      radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->screen->attribute_pos_prim_ring_tmz,
+                                RADEON_USAGE_READWRITE | RADEON_PRIO_SHADER_RINGS);
+   }
    if (ctx->border_color_buffer) {
       radeon_add_to_buffer_list(ctx, &ctx->gfx_cs, ctx->border_color_buffer,
                                 RADEON_USAGE_READ | RADEON_PRIO_BORDER_COLORS);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index a589ceefd58..5ed5163953b 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1001,6 +1001,7 @@ void si_destroy_screen(struct pipe_screen *pscreen)
    }
 
    si_resource_reference(&sscreen->attribute_pos_prim_ring, NULL);
+   si_resource_reference(&sscreen->attribute_pos_prim_ring_tmz, NULL);
    pipe_resource_reference(&sscreen->tess_rings, NULL);
    pipe_resource_reference(&sscreen->tess_rings_tmz, NULL);
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index c1630cec1ef..67e9d350528 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -661,6 +661,7 @@ struct si_screen {
    struct util_vertex_state_cache vertex_state_cache;
 
    struct si_resource *attribute_pos_prim_ring;
+   struct si_resource *attribute_pos_prim_ring_tmz;
 
    simple_mtx_t tess_ring_lock;
    struct pipe_resource *tess_rings;
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
index b7280294f5c..ed2babf5963 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
@@ -5096,7 +5096,9 @@ static void si_emit_spi_ge_ring_state(struct si_context *sctx, unsigned index)
       si_cp_release_acquire_mem_pws(sctx, &sctx->gfx_cs, V_028A90_BOTTOM_OF_PIPE_TS, 0,
                                     V_580_CP_ME, 0);
 
-      uint64_t attr_address = sscreen->attribute_pos_prim_ring->gpu_address;
+      uint64_t attr_address = sctx->ws->cs_is_secure(&sctx->gfx_cs) ?
+         sscreen->attribute_pos_prim_ring_tmz->gpu_address :
+         sscreen->attribute_pos_prim_ring->gpu_address;
       assert((attr_address >> 32) == sscreen->info.address32_hi);
 
       radeon_begin(&sctx->gfx_cs);