From 75eb0d2891c2eb7574bd943a6a40493484047b48 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 21 Dec 2022 20:17:13 -0800 Subject: [PATCH] freedreno/ir3: Allow isam for non-bindless ssbo loads We already had the infrastructure for this, dating back to a5xx, so this is low hanging fruit to hit the faster isam path. Signed-off-by: Rob Clark Part-of: --- src/freedreno/ci/freedreno-a618-fails.txt | 1 - src/freedreno/ci/freedreno-a630-fails.txt | 1 - src/freedreno/ir3/ir3_compiler_nir.c | 15 +++++++++------ src/gallium/drivers/freedreno/a6xx/fd6_context.c | 2 +- 4 files changed, 10 insertions(+), 9 deletions(-) diff --git a/src/freedreno/ci/freedreno-a618-fails.txt b/src/freedreno/ci/freedreno-a618-fails.txt index 51d67defb80..38fe35aa913 100644 --- a/src/freedreno/ci/freedreno-a618-fails.txt +++ b/src/freedreno/ci/freedreno-a618-fails.txt @@ -8,7 +8,6 @@ KHR-GL45.gpu_shader_fp64.builtin.mod_dvec4,Fail KHR-GL45.shader_subroutine.control_flow_and_returned_subroutine_values_used_as_subroutine_input,Fail KHR-GL45.shader_image_load_store.basic-allFormats-store,Fail KHR-GL45.shader_image_load_store.basic-allTargets-store,Fail -KHR-GL45.shader_image_load_store.non-layered_binding,Fail KHR-GL45.shading_language_420pack.binding_images,Fail KHR-GL45.compute_shader.conditional-dispatching,Fail KHR-GL45.vertex_attrib_binding.advanced-largeStrideAndOffsetsNewAndLegacyAPI,Fail diff --git a/src/freedreno/ci/freedreno-a630-fails.txt b/src/freedreno/ci/freedreno-a630-fails.txt index 69b7a3509f0..d3bcd84dbeb 100644 --- a/src/freedreno/ci/freedreno-a630-fails.txt +++ b/src/freedreno/ci/freedreno-a630-fails.txt @@ -8,7 +8,6 @@ KHR-GL45.gpu_shader_fp64.builtin.mod_dvec4,Fail KHR-GL45.shader_subroutine.control_flow_and_returned_subroutine_values_used_as_subroutine_input,Fail KHR-GL45.shader_image_load_store.basic-allFormats-store,Fail KHR-GL45.shader_image_load_store.basic-allTargets-store,Fail -KHR-GL45.shader_image_load_store.non-layered_binding,Fail KHR-GL45.shading_language_420pack.binding_images,Fail KHR-GL45.compute_shader.conditional-dispatching,Fail KHR-GL45.vertex_attrib_binding.advanced-largeStrideAndOffsetsNewAndLegacyAPI,Fail diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 3d2109f8ee7..45cd8647814 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -1337,7 +1337,7 @@ struct tex_src_info { * to handle with the image_mapping table.. */ static struct tex_src_info -get_image_ssbo_samp_tex_src(struct ir3_context *ctx, nir_src *src) +get_image_ssbo_samp_tex_src(struct ir3_context *ctx, nir_src *src, bool image) { struct ir3_block *b = ctx->block; struct tex_src_info info = {0}; @@ -1382,9 +1382,13 @@ get_image_ssbo_samp_tex_src(struct ir3_context *ctx, nir_src *src) } else { info.flags |= IR3_INSTR_S2EN; unsigned slot = nir_src_as_uint(*src); - unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot); + unsigned tex_idx = image ? + ir3_image_to_tex(&ctx->so->image_mapping, slot) : + ir3_ssbo_to_tex(&ctx->so->image_mapping, slot); struct ir3_instruction *texture, *sampler; + ctx->so->num_samp = MAX2(ctx->so->num_samp, tex_idx + 1); + texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16); sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16); @@ -1440,7 +1444,7 @@ emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr, } struct ir3_block *b = ctx->block; - struct tex_src_info info = get_image_ssbo_samp_tex_src(ctx, &intr->src[0]); + struct tex_src_info info = get_image_ssbo_samp_tex_src(ctx, &intr->src[0], true); struct ir3_instruction *sam; struct ir3_instruction *const *src0 = ir3_get_src(ctx, &intr->src[1]); struct ir3_instruction *coords[4]; @@ -1482,7 +1486,7 @@ emit_intrinsic_image_size_tex(struct ir3_context *ctx, struct ir3_instruction **dst) { struct ir3_block *b = ctx->block; - struct tex_src_info info = get_image_ssbo_samp_tex_src(ctx, &intr->src[0]); + struct tex_src_info info = get_image_ssbo_samp_tex_src(ctx, &intr->src[0], true); struct ir3_instruction *sam, *lod; unsigned flags, ncoords = ir3_get_image_coords(intr, &flags); type_t dst_type = nir_dest_bit_size(intr->dest) == 16 ? TYPE_U16 : TYPE_U32; @@ -1526,7 +1530,6 @@ emit_intrinsic_load_ssbo(struct ir3_context *ctx, { /* Note: isam currently can't handle vectorized loads/stores */ if (!(nir_intrinsic_access(intr) & ACCESS_CAN_REORDER) || - !ir3_bindless_resource(intr->src[0]) || intr->dest.ssa.num_components > 1) { ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst); return; @@ -1535,7 +1538,7 @@ emit_intrinsic_load_ssbo(struct ir3_context *ctx, struct ir3_block *b = ctx->block; struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[2])[0]; struct ir3_instruction *coords = ir3_collect(b, offset, create_immed(b, 0)); - struct tex_src_info info = get_image_ssbo_samp_tex_src(ctx, &intr->src[0]); + struct tex_src_info info = get_image_ssbo_samp_tex_src(ctx, &intr->src[0], false); unsigned num_components = intr->dest.ssa.num_components; struct ir3_instruction *sam = diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_context.c b/src/gallium/drivers/freedreno/a6xx/fd6_context.c index f327031e505..2eff221eff9 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_context.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_context.c @@ -161,7 +161,7 @@ setup_state_map(struct fd_context *ctx) BIT(FD6_GROUP_BLEND)); fd_context_add_map(ctx, FD_DIRTY_BLEND_COLOR, BIT(FD6_GROUP_BLEND_COLOR)); fd_context_add_map(ctx, FD_DIRTY_SSBO | FD_DIRTY_IMAGE | FD_DIRTY_PROG, - BIT(FD6_GROUP_IBO)); + BIT(FD6_GROUP_IBO) | BIT(FD6_GROUP_FS_TEX)); fd_context_add_map(ctx, FD_DIRTY_PROG, BIT(FD6_GROUP_VS_TEX) | BIT(FD6_GROUP_HS_TEX) | BIT(FD6_GROUP_DS_TEX) | BIT(FD6_GROUP_GS_TEX) |