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i965: Set MOCS for 3DSTATE_INDEX_BUFFER on Gfx6/7 as well.

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For some reason we were only setting this on Gfx8+.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
This commit is contained in:
Kenneth Graunke 2021-10-20 00:25:47 -07:00 • committed by Marge Bot
parent ab44a54646
commit 75e86afb50
1 changed files with 4 additions and 1 deletions
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5
src/mesa/drivers/dri/i965/genX_state_upload.c
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@ -862,6 +862,10 @@ genX(emit_index_buffer)(struct brw_context *brw)
#endif
ib.IndexFormat = brw_get_index_type(1 << index_buffer->index_size_shift);
#if GFX_VER >= 6
ib.MOCS = brw_mocs(&brw->isl_dev, brw->ib.bo);
#endif
/* The VF cache designers apparently cut corners, and made the cache
* only consider the bottom 32 bits of memory addresses. If you happen
* to have two index buffers which get placed exactly 4 GiB apart and
@ -871,7 +875,6 @@ genX(emit_index_buffer)(struct brw_context *brw)
*/
ib.BufferStartingAddress = ro_32_bo(brw->ib.bo, 0);
#if GFX_VER >= 8
ib.MOCS = brw_mocs(&brw->isl_dev, brw->ib.bo);
ib.BufferSize = brw->ib.size;
#else
ib.BufferEndingAddress = ro_bo(brw->ib.bo, brw->ib.size - 1);