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https://gitlab.freedesktop.org/mesa/mesa.git
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i965: Validate "Region Alignment Rules"
This commit is contained in:
Matt Turner
parent
f817d132c1
commit
75b7f5a269
2 changed files with 697 additions and 1 deletions
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@ -45,6 +45,7 @@ cat(struct string *dest, const struct string src)
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#define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
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#define error(str) "\tERROR: " str "\n"
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#define ERROR_INDENT "\t "
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#define ERROR(msg) ERROR_IF(true, msg)
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#define ERROR_IF(cond, msg) \
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@ -104,6 +105,22 @@ src0_is_grf(const struct gen_device_info *devinfo, const brw_inst *inst)
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return brw_inst_src0_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE;
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}
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static bool
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src0_has_scalar_region(const struct gen_device_info *devinfo, const brw_inst *inst)
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{
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return brw_inst_src0_vstride(devinfo, inst) == BRW_VERTICAL_STRIDE_0 &&
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brw_inst_src0_width(devinfo, inst) == BRW_WIDTH_1 &&
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brw_inst_src0_hstride(devinfo, inst) == BRW_HORIZONTAL_STRIDE_0;
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}
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static bool
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src1_has_scalar_region(const struct gen_device_info *devinfo, const brw_inst *inst)
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{
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return brw_inst_src1_vstride(devinfo, inst) == BRW_VERTICAL_STRIDE_0 &&
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brw_inst_src1_width(devinfo, inst) == BRW_WIDTH_1 &&
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brw_inst_src1_hstride(devinfo, inst) == BRW_HORIZONTAL_STRIDE_0;
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}
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static unsigned
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num_sources_from_inst(const struct gen_device_info *devinfo,
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const brw_inst *inst)
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@ -327,6 +344,26 @@ execution_type(const struct gen_device_info *devinfo, const brw_inst *inst)
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return BRW_HW_REG_TYPE_F;
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}
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/**
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* Returns whether a region is packed
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*
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* A region is packed if its elements are adjacent in memory, with no
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* intervening space, no overlap, and no replicated values.
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*/
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static bool
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is_packed(unsigned vstride, unsigned width, unsigned hstride)
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{
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if (vstride == width) {
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if (vstride == 1) {
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return hstride == 0;
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} else {
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return hstride == 1;
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}
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}
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return false;
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}
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/**
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* Checks restrictions listed in "General Restrictions Based on Operand Types"
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* in the "Register Region Restrictions" section.
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@ -557,6 +594,376 @@ general_restrictions_on_region_parameters(const struct gen_device_info *devinfo,
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return error_msg;
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}
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/**
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* Creates an \p access_mask for an \p exec_size, \p element_size, and a region
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*
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* An \p access_mask is a 32-element array of uint64_t, where each uint64_t is
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* a bitmask of bytes accessed by the region.
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*
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* For instance the access mask of the source gX.1<4,2,2>F in an exec_size = 4
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* instruction would be
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*
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* access_mask[0] = 0x00000000000000F0
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* access_mask[1] = 0x000000000000F000
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* access_mask[2] = 0x0000000000F00000
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* access_mask[3] = 0x00000000F0000000
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* access_mask[4-31] = 0
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*
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* because the first execution channel accesses bytes 7-4 and the second
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* execution channel accesses bytes 15-12, etc.
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*/
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static void
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align1_access_mask(uint64_t access_mask[static 32],
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unsigned exec_size, unsigned element_size, unsigned subreg,
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unsigned vstride, unsigned width, unsigned hstride)
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{
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const uint64_t mask = (1 << element_size) - 1;
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unsigned rowbase = subreg;
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unsigned element = 0;
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for (int y = 0; y < exec_size / width; y++) {
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unsigned offset = rowbase;
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for (int x = 0; x < width; x++) {
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access_mask[element++] = mask << offset;
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offset += hstride * element_size;
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}
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rowbase += vstride * element_size;
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}
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assert(element == 0 || element == exec_size);
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}
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/**
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* Returns the number of registers accessed according to the \p access_mask
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*/
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static int
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registers_read(const uint64_t access_mask[static 32])
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{
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int regs_read = 0;
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for (unsigned i = 0; i < 32; i++) {
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if (access_mask[i] > 0xFFFFFFFF) {
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return 2;
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} else if (access_mask[i]) {
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regs_read = 1;
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}
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}
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return regs_read;
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}
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/**
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* Checks restrictions listed in "Region Alignment Rules" in the "Register
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* Region Restrictions" section.
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*/
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static struct string
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region_alignment_rules(const struct gen_device_info *devinfo,
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const brw_inst *inst)
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{
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const struct opcode_desc *desc =
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brw_opcode_desc(devinfo, brw_inst_opcode(devinfo, inst));
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unsigned num_sources = num_sources_from_inst(devinfo, inst);
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unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst);
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uint64_t dst_access_mask[32], src0_access_mask[32], src1_access_mask[32];
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struct string error_msg = { .str = NULL, .len = 0 };
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if (num_sources == 3)
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return (struct string){};
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if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16)
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return (struct string){};
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if (inst_is_send(devinfo, inst))
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return (struct string){};
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memset(dst_access_mask, 0, sizeof(dst_access_mask));
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memset(src0_access_mask, 0, sizeof(src0_access_mask));
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memset(src1_access_mask, 0, sizeof(src1_access_mask));
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for (unsigned i = 0; i < num_sources; i++) {
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unsigned vstride, width, hstride, element_size, subreg;
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/* In Direct Addressing mode, a source cannot span more than 2 adjacent
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* GRF registers.
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*/
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#define DO_SRC(n) \
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if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \
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BRW_ADDRESS_DIRECT) \
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continue; \
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\
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if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
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BRW_IMMEDIATE_VALUE) \
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continue; \
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\
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vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
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(1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
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width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
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hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
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(1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
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element_size = brw_element_size(devinfo, inst, src ## n); \
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subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
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align1_access_mask(src ## n ## _access_mask, \
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exec_size, element_size, subreg, \
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vstride, width, hstride)
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if (i == 0) {
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DO_SRC(0);
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} else if (i == 1) {
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DO_SRC(1);
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}
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#undef DO_SRC
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unsigned num_vstride = exec_size / width;
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unsigned num_hstride = width;
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unsigned vstride_elements = (num_vstride - 1) * vstride;
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unsigned hstride_elements = (num_hstride - 1) * hstride;
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unsigned offset = (vstride_elements + hstride_elements) * element_size +
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subreg;
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ERROR_IF(offset >= 64,
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"A source cannot span more than 2 adjacent GRF registers");
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}
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if (desc->ndst == 0 || dst_is_null(devinfo, inst))
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return error_msg;
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unsigned stride = 1 << (brw_inst_dst_hstride(devinfo, inst) - 1);
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unsigned element_size = brw_element_size(devinfo, inst, dst);
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unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
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unsigned offset = ((exec_size - 1) * stride * element_size) + subreg;
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ERROR_IF(offset >= 64,
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"A destination cannot span more than 2 adjacent GRF registers");
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if (error_msg.str)
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return error_msg;
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align1_access_mask(dst_access_mask, exec_size, element_size, subreg,
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exec_size == 1 ? 0 : exec_size * stride,
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exec_size == 1 ? 1 : exec_size,
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exec_size == 1 ? 0 : stride);
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unsigned dst_regs = registers_read(dst_access_mask);
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unsigned src0_regs = registers_read(src0_access_mask);
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unsigned src1_regs = registers_read(src1_access_mask);
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/* The SNB, IVB, HSW, BDW, and CHV PRMs say:
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*
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* When an instruction has a source region spanning two registers and a
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* destination region contained in one register, the number of elements
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* must be the same between two sources and one of the following must be
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* true:
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*
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* 1. The destination region is entirely contained in the lower OWord
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* of a register.
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* 2. The destination region is entirely contained in the upper OWord
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* of a register.
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* 3. The destination elements are evenly split between the two OWords
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* of a register.
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*/
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if (devinfo->gen <= 8) {
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if (dst_regs == 1 && (src0_regs == 2 || src1_regs == 2)) {
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unsigned upper_oword_writes = 0, lower_oword_writes = 0;
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for (unsigned i = 0; i < exec_size; i++) {
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if (dst_access_mask[i] > 0x0000FFFF) {
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upper_oword_writes++;
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} else {
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assert(dst_access_mask[i] != 0);
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lower_oword_writes++;
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}
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}
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ERROR_IF(lower_oword_writes != 0 &&
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upper_oword_writes != 0 &&
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upper_oword_writes != lower_oword_writes,
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"Writes must be to only one OWord or "
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"evenly split between OWords");
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}
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}
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/* The IVB and HSW PRMs say:
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*
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* When an instruction has a source region that spans two registers and
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* the destination spans two registers, the destination elements must be
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* evenly split between the two registers [...]
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*
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* The SNB PRM contains similar wording (but written in a much more
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* confusing manner).
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*
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* The BDW PRM says:
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*
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* When destination spans two registers, the source may be one or two
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* registers. The destination elements must be evenly split between the
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* two registers.
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*
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* The SKL PRM says:
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*
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* When destination of MATH instruction spans two registers, the
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* destination elements must be evenly split between the two registers.
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*
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* It is not known whether this restriction applies to KBL other Gens after
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* SKL.
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*/
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if (devinfo->gen <= 8 ||
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brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MATH) {
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/* Nothing explicitly states that on Gen < 8 elements must be evenly
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* split between two destination registers in the two exceptional
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* source-region-spans-one-register cases, but since Broadwell requires
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* evenly split writes regardless of source region, we assume that it was
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* an oversight and require it.
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*/
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if (dst_regs == 2) {
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unsigned upper_reg_writes = 0, lower_reg_writes = 0;
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for (unsigned i = 0; i < exec_size; i++) {
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if (dst_access_mask[i] > 0xFFFFFFFF) {
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upper_reg_writes++;
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} else {
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assert(dst_access_mask[i] != 0);
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lower_reg_writes++;
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}
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}
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ERROR_IF(upper_reg_writes != lower_reg_writes,
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"Writes must be evenly split between the two "
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"destination registers");
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}
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}
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/* The IVB and HSW PRMs say:
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*
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* When an instruction has a source region that spans two registers and
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* the destination spans two registers, the destination elements must be
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* evenly split between the two registers and each destination register
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* must be entirely derived from one source register.
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*
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* Note: In such cases, the regioning parameters must ensure that the
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* offset from the two source registers is the same.
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*
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* The SNB PRM contains similar wording (but written in a much more
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* confusing manner).
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*
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* There are effectively three rules stated here:
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*
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* For an instruction with a source and a destination spanning two
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* registers,
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*
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* (1) destination elements must be evenly split between the two
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* registers
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* (2) all destination elements in a register must be derived
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* from one source register
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* (3) the offset (i.e. the starting location in each of the two
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* registers spanned by a region) must be the same in the two
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* registers spanned by a region
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*
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* It is impossible to violate rule (1) without violating (2) or (3), so we
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* do not attempt to validate it.
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*/
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if (devinfo->gen <= 7 && dst_regs == 2) {
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for (unsigned i = 0; i < num_sources; i++) {
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#define DO_SRC(n) \
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if (src ## n ## _regs <= 1) \
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continue; \
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\
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for (unsigned i = 0; i < exec_size; i++) { \
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if ((dst_access_mask[i] > 0xFFFFFFFF) != \
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(src ## n ## _access_mask[i] > 0xFFFFFFFF)) { \
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ERROR("Each destination register must be entirely derived " \
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"from one source register"); \
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break; \
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} \
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} \
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\
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unsigned offset_0 = \
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brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
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unsigned offset_1 = offset_0; \
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\
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for (unsigned i = 0; i < exec_size; i++) { \
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if (src ## n ## _access_mask[i] > 0xFFFFFFFF) { \
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offset_1 = __builtin_ctzll(src ## n ## _access_mask[i]) - 32; \
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break; \
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} \
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} \
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\
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ERROR_IF(offset_0 != offset_1, \
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"The offset from the two source registers " \
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"must be the same")
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if (i == 0) {
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DO_SRC(0);
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} else if (i == 1) {
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DO_SRC(1);
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}
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#undef DO_SRC
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}
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}
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/* The IVB and HSW PRMs say:
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*
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* When destination spans two registers, the source MUST span two
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* registers. The exception to the above rule:
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* 1. When source is scalar, the source registers are not
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* incremented.
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* 2. When source is packed integer Word and destination is packed
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* integer DWord, the source register is not incremented by the
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* source sub register is incremented.
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*
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* The SNB PRM does not contain this rule, but the internal documentation
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* indicates that it applies to SNB as well. We assume that the rule applies
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* to Gen <= 5 although their PRMs do not state it.
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*
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* While the documentation explicitly says in exception (2) that the
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* destination must be an integer DWord, the hardware allows at least a
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* float destination type as well. We emit such instructions from
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*
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* fs_visitor::emit_interpolation_setup_gen6
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* fs_visitor::emit_fragcoord_interpolation
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*
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* and have for years with no ill effects.
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*
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* Additionally the simulator source code indicates that the real condition
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* is that the size of the destination type is 4 bytes.
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*/
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if (devinfo->gen <= 7 && dst_regs == 2) {
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bool dst_is_packed_dword =
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is_packed(exec_size * stride, exec_size, stride) &&
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brw_element_size(devinfo, inst, dst) == 4;
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for (unsigned i = 0; i < num_sources; i++) {
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#define DO_SRC(n) \
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unsigned vstride, width, hstride; \
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vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
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(1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
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width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
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hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
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(1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
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bool src ## n ## _is_packed_word = \
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is_packed(vstride, width, hstride) && \
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(brw_inst_src ## n ## _reg_type(devinfo, inst) == BRW_HW_REG_TYPE_W || \
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brw_inst_src ## n ## _reg_type(devinfo, inst) == BRW_HW_REG_TYPE_UW); \
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\
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ERROR_IF(src ## n ## _regs == 1 && \
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!src ## n ## _has_scalar_region(devinfo, inst) && \
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!(dst_is_packed_dword && src ## n ## _is_packed_word), \
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"When the destination spans two registers, the source must " \
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"span two registers\n" ERROR_INDENT "(exceptions for scalar " \
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"source and packed-word to packed-dword expansion)")
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if (i == 0) {
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DO_SRC(0);
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} else if (i == 1) {
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DO_SRC(1);
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}
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#undef DO_SRC
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}
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}
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return error_msg;
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}
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bool
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brw_validate_instructions(const struct brw_codegen *p, int start_offset,
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struct annotation_info *annotation)
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@ -577,6 +984,7 @@ brw_validate_instructions(const struct brw_codegen *p, int start_offset,
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CHECK(send_restrictions);
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CHECK(general_restrictions_based_on_operand_types);
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CHECK(general_restrictions_on_region_parameters);
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CHECK(region_alignment_rules);
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}
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||||
|
||||
if (error_msg.str && annotation) {
|
||||
|
|
|
|||
|
|
@ -468,3 +468,291 @@ TEST_P(validation_test, vstride_on_align16_must_be_0_or_4)
|
|||
clear_instructions(p);
|
||||
}
|
||||
}
|
||||
|
||||
/* In Direct Addressing mode, a source cannot span more than 2 adjacent GRF
|
||||
* registers.
|
||||
*/
|
||||
TEST_P(validation_test, source_cannot_span_more_than_2_registers)
|
||||
{
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_32);
|
||||
brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
|
||||
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8);
|
||||
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
|
||||
|
||||
EXPECT_FALSE(validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
|
||||
brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
|
||||
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8);
|
||||
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
|
||||
brw_inst_set_src1_da1_subreg_nr(&devinfo, last_inst, 2);
|
||||
|
||||
EXPECT_TRUE(validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
|
||||
|
||||
EXPECT_TRUE(validate(p));
|
||||
}
|
||||
|
||||
/* A destination cannot span more than 2 adjacent GRF registers. */
|
||||
TEST_P(validation_test, destination_cannot_span_more_than_2_registers)
|
||||
{
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_32);
|
||||
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
|
||||
brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
|
||||
EXPECT_FALSE(validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_8);
|
||||
brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 6);
|
||||
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_4);
|
||||
brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
|
||||
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
|
||||
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
|
||||
brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
|
||||
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
|
||||
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
|
||||
|
||||
EXPECT_TRUE(validate(p));
|
||||
}
|
||||
|
||||
TEST_P(validation_test, src_region_spans_two_regs_dst_region_spans_one)
|
||||
{
|
||||
/* Writes to dest are to the lower OWord */
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
|
||||
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
|
||||
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
|
||||
|
||||
EXPECT_TRUE(validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
|
||||
/* Writes to dest are to the upper OWord */
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 16);
|
||||
brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
|
||||
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
|
||||
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
|
||||
|
||||
EXPECT_TRUE(validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
|
||||
/* Writes to dest are evenly split between OWords */
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
|
||||
brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
|
||||
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_8);
|
||||
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
|
||||
|
||||
EXPECT_TRUE(validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
|
||||
/* Writes to dest are uneven between OWords */
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4);
|
||||
brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 10);
|
||||
brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
|
||||
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
|
||||
brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_16);
|
||||
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2);
|
||||
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
|
||||
|
||||
if (devinfo.gen >= 9) {
|
||||
EXPECT_TRUE(validate(p));
|
||||
} else {
|
||||
EXPECT_FALSE(validate(p));
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, dst_elements_must_be_evenly_split_between_registers)
|
||||
{
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 4);
|
||||
|
||||
if (devinfo.gen >= 9) {
|
||||
EXPECT_TRUE(validate(p));
|
||||
} else {
|
||||
EXPECT_FALSE(validate(p));
|
||||
}
|
||||
|
||||
clear_instructions(p);
|
||||
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
|
||||
|
||||
EXPECT_TRUE(validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
|
||||
if (devinfo.gen >= 6) {
|
||||
gen6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null);
|
||||
|
||||
EXPECT_TRUE(validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
|
||||
gen6_math(p, g0, BRW_MATH_FUNCTION_SIN, g0, null);
|
||||
brw_inst_set_dst_da1_subreg_nr(&devinfo, last_inst, 4);
|
||||
|
||||
EXPECT_FALSE(validate(p));
|
||||
}
|
||||
}
|
||||
|
||||
TEST_P(validation_test, two_src_two_dst_source_offsets_must_be_same)
|
||||
{
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4);
|
||||
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_4);
|
||||
brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 16);
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_2);
|
||||
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1);
|
||||
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
|
||||
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
|
||||
|
||||
if (devinfo.gen <= 7) {
|
||||
EXPECT_FALSE(validate(p));
|
||||
} else {
|
||||
EXPECT_TRUE(validate(p));
|
||||
}
|
||||
|
||||
clear_instructions(p);
|
||||
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_4);
|
||||
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_4);
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1);
|
||||
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_8);
|
||||
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_2);
|
||||
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
|
||||
|
||||
EXPECT_TRUE(validate(p));
|
||||
}
|
||||
|
||||
#if 0
|
||||
TEST_P(validation_test, two_src_two_dst_each_dst_must_be_derived_from_one_src)
|
||||
{
|
||||
// mov (16) r10.0<2>:w r12.4<4;4,1>:w
|
||||
|
||||
brw_MOV(p, g0, g0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
|
||||
brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
|
||||
brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src0_da1_subreg_nr(&devinfo, last_inst, 8);
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_4);
|
||||
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_4);
|
||||
|
||||
EXPECT_FALSE(validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
|
||||
#if 0
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_src1_da1_subreg_nr(&devinfo, last_inst, 16);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_4);
|
||||
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_4);
|
||||
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_1);
|
||||
|
||||
EXPECT_FALSE(validate(p));
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
TEST_P(validation_test, one_src_two_dst)
|
||||
{
|
||||
struct brw_reg g0_0 = brw_vec1_grf(0, 0);
|
||||
|
||||
brw_ADD(p, g0, g0_0, g0_0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
|
||||
|
||||
EXPECT_TRUE(validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
|
||||
brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_D);
|
||||
brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
|
||||
EXPECT_TRUE(validate(p));
|
||||
|
||||
clear_instructions(p);
|
||||
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
|
||||
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
|
||||
brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src1_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
|
||||
brw_inst_set_src1_width(&devinfo, last_inst, BRW_WIDTH_1);
|
||||
brw_inst_set_src1_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
|
||||
|
||||
if (devinfo.gen >= 8) {
|
||||
EXPECT_TRUE(validate(p));
|
||||
} else {
|
||||
EXPECT_FALSE(validate(p));
|
||||
}
|
||||
|
||||
clear_instructions(p);
|
||||
|
||||
brw_ADD(p, g0, g0, g0);
|
||||
brw_inst_set_exec_size(&devinfo, last_inst, BRW_EXECUTE_16);
|
||||
brw_inst_set_dst_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_2);
|
||||
brw_inst_set_dst_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src0_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_0);
|
||||
brw_inst_set_src0_width(&devinfo, last_inst, BRW_WIDTH_1);
|
||||
brw_inst_set_src0_hstride(&devinfo, last_inst, BRW_HORIZONTAL_STRIDE_0);
|
||||
brw_inst_set_src1_reg_type(&devinfo, last_inst, BRW_HW_REG_TYPE_W);
|
||||
|
||||
if (devinfo.gen >= 8) {
|
||||
EXPECT_TRUE(validate(p));
|
||||
} else {
|
||||
EXPECT_FALSE(validate(p));
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue