fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-09 08:58:02 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

anv: limit RT writes to number of color outputs

Browse source 
Not doing so crates skews occlusion queries. Fixes Zink's piglit
occlusion_query tests.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a4f502de32 ("anv: fix VK_DYNAMIC_STATE_COLOR_WRITE_ENABLE_EXT state")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6205
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15740>
(cherry picked from commit 5d05ffa465)
This commit is contained in:
Lionel Landwerlin 2022-04-04 23:40:24 +03:00 • committed by Dylan Baker
parent ac10f5a3ab
commit 755fe3ee27
2 changed files with 8 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -220,7 +220,7 @@
"description": "anv: limit RT writes to number of color outputs",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "a4f502de3228ec37dfcaa38225077ec3709d74ea"
},

11
src/intel/vulkan/anv_pipeline.c
View file

@ -485,8 +485,8 @@ populate_wm_prog_key(const struct anv_graphics_pipeline *pipeline,
assert(rendering_info->colorAttachmentCount <= MAX_RTS);
/* Consider all inputs as valid until look at the NIR variables. */
key->color_outputs_valid = (1u << MAX_RTS) - 1;
key->nr_color_regions = MAX_RTS;
key->color_outputs_valid = (1u << rendering_info->colorAttachmentCount) - 1;
key->nr_color_regions = rendering_info->colorAttachmentCount;
/* To reduce possible shader recompilations we would need to know if
* there is a SampleMask output variable to compute if we should emit
@ -1116,7 +1116,8 @@ anv_pipeline_compile_mesh(const struct brw_compiler *compiler,
static void
anv_pipeline_link_fs(const struct brw_compiler *compiler,
struct anv_pipeline_stage *stage)
struct anv_pipeline_stage *stage,
const VkPipelineRenderingCreateInfo *rendering_info)
{
/* Initially the valid outputs value is set to all possible render targets
* valid (see populate_wm_prog_key()), before we look at the shader
@ -1135,6 +1136,8 @@ anv_pipeline_link_fs(const struct brw_compiler *compiler,
stage->key.wm.color_outputs_valid |= BITFIELD_RANGE(rt, array_len);
}
stage->key.wm.color_outputs_valid &=
(1u << rendering_info->colorAttachmentCount) - 1;
stage->key.wm.nr_color_regions =
util_last_bit(stage->key.wm.color_outputs_valid);
@ -1680,7 +1683,7 @@ anv_pipeline_compile_graphics(struct anv_graphics_pipeline *pipeline,
anv_pipeline_link_mesh(compiler, &stages[s], next_stage);
break;
case MESA_SHADER_FRAGMENT:
anv_pipeline_link_fs(compiler, &stages[s]);
anv_pipeline_link_fs(compiler, &stages[s], rendering_info);
break;
default:
unreachable("Invalid graphics shader stage");