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pvr: Implement color/depth/depth+stencil attachment clear.
The depth/depth+stencil clear was already implemented. This adds the z replication and color attachment clear branches. Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com> Reviewed-by: Frank Binns <frank.binns@imgtec.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20055>
This commit is contained in:
Karmjit Mahil
Marge Bot
parent
6e2ec31043
commit
7509e259f8
2 changed files with 325 additions and 7 deletions
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@ -27,7 +27,10 @@
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#include "pvr_clear.h"
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#include "pvr_csb.h"
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#include "pvr_formats.h"
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#include "pvr_private.h"
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#include "pvr_shader_factory.h"
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#include "pvr_static_shaders.h"
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#include "util/list.h"
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#include "vk_alloc.h"
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#include "vk_command_buffer.h"
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@ -254,6 +257,256 @@ pvr_clear_template_idx_from_aspect(VkImageAspectFlags aspect)
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}
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}
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static VkResult pvr_clear_color_attachment_static_create_consts_buffer(
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struct pvr_cmd_buffer *cmd_buffer,
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const struct pvr_shader_factory_info *shader_info,
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const uint32_t clear_color[static const PVR_CLEAR_COLOR_ARRAY_SIZE],
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ASSERTED bool uses_tile_buffer,
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struct pvr_bo **const const_shareds_buffer_out)
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{
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struct pvr_device *device = cmd_buffer->device;
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struct pvr_bo *const_shareds_buffer;
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uint32_t *buffer;
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VkResult result;
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/* TODO: This doesn't need to be aligned to slc size. Alignment to 4 is fine.
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* Change pvr_cmd_buffer_alloc_mem() to take in an alignment?
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*/
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result = pvr_cmd_buffer_alloc_mem(cmd_buffer,
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device->heaps.general_heap,
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shader_info->const_shared_regs,
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PVR_BO_ALLOC_FLAG_CPU_MAPPED,
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&const_shareds_buffer);
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if (result != VK_SUCCESS)
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return result;
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buffer = const_shareds_buffer->bo->map;
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for (uint32_t i = 0; i < PVR_CLEAR_ATTACHMENT_CONST_COUNT; i++) {
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uint32_t dest_idx = shader_info->driver_const_location_map[i];
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if (dest_idx == PVR_CLEAR_ATTACHMENT_DEST_ID_UNUSED)
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continue;
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assert(dest_idx < shader_info->const_shared_regs);
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switch (i) {
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case PVR_CLEAR_ATTACHMENT_CONST_COMPONENT_0:
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case PVR_CLEAR_ATTACHMENT_CONST_COMPONENT_1:
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case PVR_CLEAR_ATTACHMENT_CONST_COMPONENT_2:
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case PVR_CLEAR_ATTACHMENT_CONST_COMPONENT_3:
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buffer[dest_idx] = clear_color[i];
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break;
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case PVR_CLEAR_ATTACHMENT_CONST_TILE_BUFFER_UPPER:
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case PVR_CLEAR_ATTACHMENT_CONST_TILE_BUFFER_LOWER:
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assert(uses_tile_buffer);
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buffer[dest_idx] = ~0;
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pvr_finishme("Add support for tile buffer output clear.");
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break;
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default:
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unreachable("Unsupported clear attachment const type.");
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}
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}
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for (uint32_t i = 0; i < shader_info->num_static_const; i++) {
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const struct pvr_static_buffer *static_buff =
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&shader_info->static_const_buffer[i];
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assert(static_buff->dst_idx < shader_info->const_shared_regs);
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buffer[static_buff->dst_idx] = static_buff->value;
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}
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pvr_bo_cpu_unmap(device, const_shareds_buffer);
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*const_shareds_buffer_out = const_shareds_buffer;
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return VK_SUCCESS;
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}
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static VkResult pvr_clear_color_attachment_static(
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struct pvr_cmd_buffer *cmd_buffer,
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const struct usc_mrt_resource *mrt_resource,
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VkFormat format,
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uint32_t clear_color[static const PVR_CLEAR_COLOR_ARRAY_SIZE],
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uint32_t template_idx,
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uint32_t stencil,
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bool vs_has_rt_id_output)
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{
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struct pvr_device *device = cmd_buffer->device;
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ASSERTED const struct pvr_device_info *dev_info = &device->pdevice->dev_info;
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ASSERTED const bool has_eight_output_registers =
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PVR_HAS_FEATURE(dev_info, eight_output_registers);
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const struct pvr_device_static_clear_state *dev_clear_state =
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&device->static_clear_state;
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const bool uses_tile_buffer = mrt_resource->type ==
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USC_MRT_RESOURCE_TYPE_OUTPUT_REG;
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const struct pvr_pds_clear_attachment_program_info *clear_attachment_program;
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struct pvr_pds_pixel_shader_sa_program texture_program;
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uint32_t pds_state[PVR_STATIC_CLEAR_PDS_STATE_COUNT];
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const struct pvr_shader_factory_info *shader_info;
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struct pvr_static_clear_ppp_template template;
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struct pvr_bo *pds_texture_program_bo;
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struct pvr_bo *const_shareds_buffer;
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uint64_t pds_texture_program_addr;
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uint32_t out_reg_count;
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uint32_t output_offset;
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struct pvr_bo *pvr_bo;
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uint32_t program_idx;
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uint32_t *buffer;
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VkResult result;
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out_reg_count =
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DIV_ROUND_UP(pvr_get_pbe_accum_format_size_in_bytes(format), 4U);
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if (uses_tile_buffer)
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output_offset = mrt_resource->reg.offset;
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else
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output_offset = mrt_resource->mem.offset_dw;
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assert(has_eight_output_registers || out_reg_count + output_offset <= 4);
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program_idx = pvr_get_clear_attachment_program_index(out_reg_count,
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output_offset,
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uses_tile_buffer);
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shader_info = clear_attachment_collection[program_idx].info;
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result = pvr_clear_color_attachment_static_create_consts_buffer(
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cmd_buffer,
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shader_info,
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clear_color,
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uses_tile_buffer,
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&const_shareds_buffer);
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if (result != VK_SUCCESS)
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return result;
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/* clang-format off */
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texture_program = (struct pvr_pds_pixel_shader_sa_program){
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.num_texture_dma_kicks = 1,
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.texture_dma_address = {
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[0] = const_shareds_buffer->vma->dev_addr.addr,
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}
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};
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/* clang-format on */
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pvr_csb_pack (&texture_program.texture_dma_control[0],
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PDSINST_DOUT_FIELDS_DOUTD_SRC1,
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doutd_src1) {
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doutd_src1.dest = PVRX(PDSINST_DOUTD_DEST_COMMON_STORE);
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doutd_src1.bsize = shader_info->const_shared_regs;
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}
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clear_attachment_program =
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&dev_clear_state->pds_clear_attachment_program_info[program_idx];
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/* TODO: This doesn't need to be aligned to slc size. Alignment to 4 is fine.
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* Change pvr_cmd_buffer_alloc_mem() to take in an alignment?
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*/
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result = pvr_cmd_buffer_alloc_mem(
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cmd_buffer,
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device->heaps.pds_heap,
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clear_attachment_program->texture_program_data_size,
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PVR_BO_ALLOC_FLAG_CPU_MAPPED,
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&pds_texture_program_bo);
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if (result != VK_SUCCESS) {
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list_del(&const_shareds_buffer->link);
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pvr_bo_free(device, const_shareds_buffer);
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return result;
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}
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buffer = pds_texture_program_bo->bo->map;
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pds_texture_program_addr = pds_texture_program_bo->vma->dev_addr.addr -
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device->heaps.pds_heap->base_addr.addr;
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pvr_pds_generate_pixel_shader_sa_texture_state_data(
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&texture_program,
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buffer,
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&device->pdevice->dev_info);
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pvr_bo_cpu_unmap(device, pds_texture_program_bo);
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pvr_csb_pack (&pds_state[PVR_STATIC_CLEAR_PPP_PDS_TYPE_SHADERBASE],
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TA_STATE_PDS_SHADERBASE,
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shaderbase) {
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shaderbase.addr = clear_attachment_program->pixel_program_offset;
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}
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pvr_csb_pack (&pds_state[PVR_STATIC_CLEAR_PPP_PDS_TYPE_TEXUNICODEBASE],
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TA_STATE_PDS_TEXUNICODEBASE,
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texunicodebase) {
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texunicodebase.addr = clear_attachment_program->texture_program_offset;
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}
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pvr_csb_pack (&pds_state[PVR_STATIC_CLEAR_PPP_PDS_TYPE_SIZEINFO1],
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TA_STATE_PDS_SIZEINFO1,
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sizeinfo1) {
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sizeinfo1.pds_texturestatesize = DIV_ROUND_UP(
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clear_attachment_program->texture_program_data_size,
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PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEXTURESTATESIZE_UNIT_SIZE));
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sizeinfo1.pds_tempsize =
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DIV_ROUND_UP(clear_attachment_program->texture_program_pds_temps_count,
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PVRX(TA_STATE_PDS_SIZEINFO1_PDS_TEMPSIZE_UNIT_SIZE));
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}
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pvr_csb_pack (&pds_state[PVR_STATIC_CLEAR_PPP_PDS_TYPE_SIZEINFO2],
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TA_STATE_PDS_SIZEINFO2,
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sizeinfo2) {
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sizeinfo2.usc_sharedsize =
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DIV_ROUND_UP(shader_info->const_shared_regs,
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PVRX(TA_STATE_PDS_SIZEINFO2_USC_SHAREDSIZE_UNIT_SIZE));
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}
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/* Dummy coefficient loading program. */
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pds_state[PVR_STATIC_CLEAR_PPP_PDS_TYPE_VARYINGBASE] = 0;
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pvr_csb_pack (&pds_state[PVR_STATIC_CLEAR_PPP_PDS_TYPE_TEXTUREDATABASE],
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TA_STATE_PDS_TEXTUREDATABASE,
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texturedatabase) {
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texturedatabase.addr = PVR_DEV_ADDR(pds_texture_program_addr);
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}
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template =
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cmd_buffer->device->static_clear_state.ppp_templates[template_idx];
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template.config.pds_state = &pds_state;
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template.config.ispctl.upass =
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cmd_buffer->state.render_pass_info.isp_userpass;
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if (template_idx & PVR_STATIC_CLEAR_STENCIL_BIT)
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template.config.ispa.sref = stencil;
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if (vs_has_rt_id_output) {
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template.config.output_sel.rhw_pres = true;
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template.config.output_sel.render_tgt_pres = true;
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template.config.output_sel.vtxsize = 4 + 1;
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}
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result = pvr_emit_ppp_from_template(
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&cmd_buffer->state.current_sub_cmd->gfx.control_stream,
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&template,
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&pvr_bo);
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if (result != VK_SUCCESS) {
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list_del(&pds_texture_program_bo->link);
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pvr_bo_free(device, pds_texture_program_bo);
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list_del(&const_shareds_buffer->link);
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pvr_bo_free(device, const_shareds_buffer);
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cmd_buffer->state.status = result;
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return result;
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}
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list_add(&pvr_bo->link, &cmd_buffer->bo_list);
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return VK_SUCCESS;
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}
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static void pvr_clear_attachments(struct pvr_cmd_buffer *cmd_buffer,
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uint32_t attachment_count,
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const VkClearAttachment *attachments,
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@ -266,6 +519,7 @@ static void pvr_clear_attachments(struct pvr_cmd_buffer *cmd_buffer,
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pvr_get_hw_subpass(pass, pass_info->subpass_idx);
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struct pvr_sub_cmd_gfx *sub_cmd = &cmd_buffer->state.current_sub_cmd->gfx;
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struct pvr_device_info *dev_info = &cmd_buffer->device->pdevice->dev_info;
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struct pvr_render_subpass *sub_pass = &pass->subpasses[hw_pass->index];
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bool z_replicate = hw_pass->z_replicate != -1;
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uint32_t vs_output_size_in_bytes;
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bool vs_has_rt_id_output;
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@ -299,11 +553,71 @@ static void pvr_clear_attachments(struct pvr_cmd_buffer *cmd_buffer,
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float depth;
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if (attachment->aspectMask == VK_IMAGE_ASPECT_COLOR_BIT) {
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pvr_finishme("Implement clear for color attachment.");
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uint32_t packed_clear_color[PVR_CLEAR_COLOR_ARRAY_SIZE];
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const struct usc_mrt_resource *mrt_resource;
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uint32_t global_attachment_idx;
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uint32_t local_attachment_idx;
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VkFormat format;
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local_attachment_idx = attachment->colorAttachment;
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mrt_resource = &hw_pass->setup.mrt_resources[local_attachment_idx];
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assert(local_attachment_idx < sub_pass->color_count);
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global_attachment_idx =
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sub_pass->color_attachments[local_attachment_idx];
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if (global_attachment_idx == VK_ATTACHMENT_UNUSED)
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continue;
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assert(global_attachment_idx < pass->attachment_count);
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format = pass->attachments[global_attachment_idx].vk_format;
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assert(format != VK_FORMAT_UNDEFINED);
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pvr_get_hw_clear_color(format,
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attachment->clearValue.color,
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packed_clear_color);
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result = pvr_clear_color_attachment_static(cmd_buffer,
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mrt_resource,
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format,
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packed_clear_color,
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PVR_STATIC_CLEAR_COLOR_BIT,
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0,
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vs_has_rt_id_output);
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if (result != VK_SUCCESS)
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return;
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} else if (z_replicate &&
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attachment->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT) {
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pvr_finishme("Implement clear for depth/depth+stencil attachment on "
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"z_replicate.");
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const VkClearColorValue clear_color = {
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.float32 = { [0] = attachment->clearValue.depthStencil.depth, },
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};
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const uint32_t stencil = attachment->clearValue.depthStencil.stencil;
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uint32_t packed_clear_color[PVR_CLEAR_COLOR_ARRAY_SIZE];
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const struct usc_mrt_resource *mrt_resource;
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uint32_t template_idx;
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template_idx =
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pvr_clear_template_idx_from_aspect(attachment->aspectMask);
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template_idx |= PVR_STATIC_CLEAR_COLOR_BIT;
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assert(hw_pass->z_replicate > 0);
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mrt_resource = &hw_pass->setup.mrt_resources[hw_pass->z_replicate];
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pvr_get_hw_clear_color(VK_FORMAT_R32_SFLOAT,
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clear_color,
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packed_clear_color);
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result = pvr_clear_color_attachment_static(cmd_buffer,
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mrt_resource,
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VK_FORMAT_R32_SFLOAT,
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packed_clear_color,
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template_idx,
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stencil,
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vs_has_rt_id_output);
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if (result != VK_SUCCESS)
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return;
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} else {
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struct pvr_static_clear_ppp_template template;
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uint32_t template_idx;
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@ -55,10 +55,14 @@ enum pvr_reset_query_pool_pool_const {
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/* ClearAttachments. */
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enum pvr_clear_attachment_const {
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PVR_CLEAR_ATTACHMENT_CONST_COMPONENT_0,
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PVR_CLEAR_ATTACHMENT_CONST_COMPONENT_1,
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PVR_CLEAR_ATTACHMENT_CONST_COMPONENT_2,
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PVR_CLEAR_ATTACHMENT_CONST_COMPONENT_3,
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PVR_CLEAR_ATTACHMENT_CONST_COMPONENT_0 = 0, /* Don't change. Indexes array.
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*/
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PVR_CLEAR_ATTACHMENT_CONST_COMPONENT_1 = 1, /* Don't change. Indexes array.
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*/
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PVR_CLEAR_ATTACHMENT_CONST_COMPONENT_2 = 2, /* Don't change. Indexes array.
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*/
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PVR_CLEAR_ATTACHMENT_CONST_COMPONENT_3 = 3, /* Don't change. Indexes array.
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*/
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PVR_CLEAR_ATTACHMENT_CONST_TILE_BUFFER_UPPER,
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PVR_CLEAR_ATTACHMENT_CONST_TILE_BUFFER_LOWER,
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PVR_CLEAR_ATTACHMENT_CONST_COUNT,
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