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i965/skl: Don't use the PMA depth stall workaround

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The PMA depth stall must be enabled (optimization turned off) under certain
circumstances on gen8. This was supposedly fixed for Gen9, which means we do not
need to check, or toggle the state. The hardware is supposed to enable the
hardware optimization by default, unlike BDW, so we also don't need to set it at
init. For whatever reason this improves stability on ETQW with the bug mentioned
below.

References: https://bugs.freedesktop.org/show_bug.cgi?id=89039 (doesn't fix)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Anuj Phogat <anuj.phogat@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Ben Widawsky 2015-03-25 16:52:46 -07:00
parent 9d32d35850
commit 74fd226e34
1 changed files with 6 additions and 1 deletions
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7
src/mesa/drivers/dri/i965/gen8_depth_state.c
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@ -368,6 +368,10 @@ static void
gen8_emit_pma_stall_workaround(struct brw_context *brw) gen8_emit_pma_stall_workaround(struct brw_context *brw)
{ {
uint32_t bits = 0; uint32_t bits = 0;
if (brw->gen >= 9)
return;
if (pma_fix_enable(brw)) if (pma_fix_enable(brw))
bits |= GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE; bits |= GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE;
@ -400,7 +404,8 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
return; return;
/* Disable the PMA stall fix since we're about to do a HiZ operation. */ /* Disable the PMA stall fix since we're about to do a HiZ operation. */
write_pma_stall_bits(brw, 0); if (brw->gen == 8)
write_pma_stall_bits(brw, 0);
assert(mt->first_level == 0); assert(mt->first_level == 0);
assert(mt->logical_depth0 >= 1); assert(mt->logical_depth0 >= 1);