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etnaviv: Use old set of state registers for PE configuration on GC880
While the GC880 is HALTI0, it still uses the old set of state registers for PE pipe configuration. This is another specialty of the GC880, readd the missing handling for this GPU otherwise e.g. Qt5 cube example suffers from rendering corruption with both eglfs and wayland backends. Fixes:7c46a48836("etnaviv: use new PE pipe address states on >= HALTI0") Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Marek Vasut <marex@denx.de> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19562> (cherry picked from commit20984aab0f)
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commit
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3 changed files with 5 additions and 5 deletions
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@ -382,7 +382,7 @@
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"description": "etnaviv: Use old set of state registers for PE configuration on GC880",
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"nominated": true,
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"nomination_type": 1,
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"resolution": 0,
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"resolution": 1,
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"main_sha": null,
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"because_sha": "7c46a4883625a20691a78170f8da783dc9b8a9c6"
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},
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@ -440,7 +440,7 @@ etna_emit_state(struct etna_context *ctx)
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if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
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/*0140C*/ EMIT_STATE(PE_DEPTH_NORMALIZE, ctx->framebuffer.PE_DEPTH_NORMALIZE);
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if (screen->specs.halti < 0) {
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if (screen->specs.halti < 0 || screen->model == 0x880) {
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/*01410*/ EMIT_STATE_RELOC(PE_DEPTH_ADDR, &ctx->framebuffer.PE_DEPTH_ADDR);
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}
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@ -477,7 +477,7 @@ etna_emit_state(struct etna_context *ctx)
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/*0142C*/ EMIT_STATE(PE_COLOR_FORMAT, val);
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}
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if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
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if (screen->specs.halti >= 0) {
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if (screen->specs.halti >= 0 && screen->model != 0x880) {
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/*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE);
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/*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL);
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/*01460*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(0), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[0]);
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@ -186,7 +186,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
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cbuf->surf.offset, cbuf->surf.stride * 4);
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}
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if (screen->specs.halti >= 0) {
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if (screen->specs.halti >= 0 && screen->model != 0x880) {
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/* Rendertargets on GPUs with more than a single pixel pipe must always
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* be multi-tiled, or single-buffer mode must be supported */
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assert(screen->specs.pixel_pipes == 1 ||
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@ -271,7 +271,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
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/* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
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/* merged with depth_stencil_alpha */
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if (screen->specs.halti >= 0) {
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if (screen->specs.halti >= 0 && screen->model != 0x880) {
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for (int i = 0; i < screen->specs.pixel_pipes; i++) {
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cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i];
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cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
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