diff --git a/.pick_status.json b/.pick_status.json
index 5822c87fb60..2d96fc261f5 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -2218,7 +2218,7 @@
         "description": "hasvk: add restrictions for 3DSTATE_RASTER::AntiAliasingEnable",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },
diff --git a/src/intel/vulkan_hasvk/anv_private.h b/src/intel/vulkan_hasvk/anv_private.h
index ba81eb64d0d..0367cefecc9 100644
--- a/src/intel/vulkan_hasvk/anv_private.h
+++ b/src/intel/vulkan_hasvk/anv_private.h
@@ -74,6 +74,7 @@
 #include "vk_device.h"
 #include "vk_drm_syncobj.h"
 #include "vk_enum_defines.h"
+#include "vk_format.h"
 #include "vk_framebuffer.h"
 #include "vk_graphics_state.h"
 #include "vk_image.h"
@@ -2568,6 +2569,8 @@ struct anv_cmd_graphics_state {
    uint32_t index_offset;
 
    struct vk_sample_locations_state sample_locations;
+
+   bool has_uint_rt;
 };
 
 enum anv_depth_reg_mode {
@@ -3076,6 +3079,18 @@ anv_cmd_buffer_all_color_write_masked(const struct anv_cmd_buffer *cmd_buffer)
    return true;
 }
 
+static inline void
+anv_cmd_graphic_state_update_has_uint_rt(struct anv_cmd_graphics_state *state)
+{
+   state->has_uint_rt = false;
+   for (unsigned a = 0; a < state->color_att_count; a++) {
+      if (vk_format_is_int(state->color_att[a].vk_format)) {
+         state->has_uint_rt = true;
+         break;
+      }
+   }
+}
+
 #define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage)             \
 static inline const struct brw_##prefix##_prog_data *                   \
 get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline)  \
diff --git a/src/intel/vulkan_hasvk/genX_cmd_buffer.c b/src/intel/vulkan_hasvk/genX_cmd_buffer.c
index bd8df92617e..df815c55b54 100644
--- a/src/intel/vulkan_hasvk/genX_cmd_buffer.c
+++ b/src/intel/vulkan_hasvk/genX_cmd_buffer.c
@@ -1723,6 +1723,8 @@ genX(BeginCommandBuffer)(
             inheritance_info->stencilAttachmentFormat;
 
          cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
+
+         anv_cmd_graphic_state_update_has_uint_rt(gfx);
       }
    }
 
@@ -6202,6 +6204,8 @@ void genX(CmdBeginRendering)(
       }
    }
 
+   anv_cmd_graphic_state_update_has_uint_rt(gfx);
+
    const struct anv_image_view *fsr_iview = NULL;
    const VkRenderingFragmentShadingRateAttachmentInfoKHR *fsr_att =
       vk_find_struct_const(pRenderingInfo->pNext,
diff --git a/src/intel/vulkan_hasvk/gfx7_cmd_buffer.c b/src/intel/vulkan_hasvk/gfx7_cmd_buffer.c
index 55221799f32..45fe9e9c9fc 100644
--- a/src/intel/vulkan_hasvk/gfx7_cmd_buffer.c
+++ b/src/intel/vulkan_hasvk/gfx7_cmd_buffer.c
@@ -80,8 +80,15 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
       uint32_t ms_rast_mode =
          genX(ms_rasterization_mode)(pipeline, dynamic_raster_mode);
 
+     /* From the Haswell PRM, Volume 2b, documentation for
+      * 3DSTATE_SF, "Antialiasing Enable":
+      *
+      * "This field must be disabled if any of the render targets
+      * have integer (UINT or SINT) surface format."
+      */
       bool aa_enable = anv_rasterization_aa_mode(dynamic_raster_mode,
-                                                 pipeline->line_mode);
+                                                 pipeline->line_mode) &&
+                       !cmd_buffer->state.gfx.has_uint_rt;
 
       uint32_t sf_dw[GENX(3DSTATE_SF_length)];
       struct GENX(3DSTATE_SF) sf = {
diff --git a/src/intel/vulkan_hasvk/gfx8_cmd_buffer.c b/src/intel/vulkan_hasvk/gfx8_cmd_buffer.c
index 8972a0c73fd..f0d28aca6b8 100644
--- a/src/intel/vulkan_hasvk/gfx8_cmd_buffer.c
+++ b/src/intel/vulkan_hasvk/gfx8_cmd_buffer.c
@@ -366,8 +366,20 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
                                pipeline->line_mode, dyn->rs.line.width,
                                &api_mode, &msaa_raster_enable);
 
-      bool aa_enable = anv_rasterization_aa_mode(dynamic_raster_mode,
-                                                 pipeline->line_mode);
+     /* From the Browadwell PRM, Volume 2, documentation for
+      * 3DSTATE_RASTER, "Antialiasing Enable":
+      *
+      * "This field must be disabled if any of the render targets
+      * have integer (UINT or SINT) surface format."
+      *
+      * Additionally internal documentation for Gfx12+ states:
+      *
+      * "This bit MUST not be set when NUM_MULTISAMPLES > 1 OR
+      *  FORCED_SAMPLE_COUNT > 1."
+      */
+      bool aa_enable =
+         anv_rasterization_aa_mode(dynamic_raster_mode, pipeline->line_mode) &&
+         !cmd_buffer->state.gfx.has_uint_rt;
 
       uint32_t raster_dw[GENX(3DSTATE_RASTER_length)];
       struct GENX(3DSTATE_RASTER) raster = {