diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index a183153573d..0422ca70f98 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1876,7 +1876,7 @@ radv_emit_ps_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shader
    if (cmd_buffer->state.emitted_ps_epilog == ps_epilog)
       return;
 
-   uint32_t col_format = radv_compact_spi_shader_col_format(ps_shader, ps_epilog->spi_shader_col_format);
+   uint32_t col_format = radv_compact_spi_shader_col_format(ps_epilog->spi_shader_col_format);
 
    bool need_null_export_workaround = radv_needs_null_export_workaround(device, ps_shader, 0);
    if (need_null_export_workaround && !col_format)
diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c
index 7e65f9b5877..9bde8f5c99e 100644
--- a/src/amd/vulkan/radv_pipeline_graphics.c
+++ b/src/amd/vulkan/radv_pipeline_graphics.c
@@ -170,16 +170,11 @@ format_is_float32(VkFormat format)
 }
 
 unsigned
-radv_compact_spi_shader_col_format(const struct radv_shader *ps, uint32_t spi_shader_col_format)
+radv_compact_spi_shader_col_format(uint32_t spi_shader_col_format)
 {
    unsigned value = 0, num_mrts = 0;
    unsigned i, num_targets;
 
-   /* Make sure to clear color attachments without exports because MRT holes are removed during
-    * compilation for optimal performance.
-    */
-   spi_shader_col_format &= ps->info.ps.colors_written;
-
    /* Compute the number of MRTs. */
    num_targets = DIV_ROUND_UP(util_last_bit(spi_shader_col_format), 4);
 
@@ -4072,7 +4067,11 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
    struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
    bool enable_mrt_compaction = ps && !ps->info.has_epilog && !ps->info.ps.mrt0_is_dual_src;
    if (enable_mrt_compaction) {
-      blend.spi_shader_col_format = radv_compact_spi_shader_col_format(ps, blend.spi_shader_col_format);
+      /* Make sure to clear color attachments without exports because MRT holes are removed during
+       * compilation for optimal performance.
+       */
+      blend.spi_shader_col_format =
+         radv_compact_spi_shader_col_format(blend.spi_shader_col_format & ps->info.ps.colors_written);
 
       /* In presence of MRT holes (ie. the FS exports MRT1 but not MRT0), the compiler will remap
        * them, so that only MRT0 is exported and the driver will compact SPI_SHADER_COL_FORMAT to
diff --git a/src/amd/vulkan/radv_pipeline_graphics.h b/src/amd/vulkan/radv_pipeline_graphics.h
index 9fe557161ab..16f75f2e20a 100644
--- a/src/amd/vulkan/radv_pipeline_graphics.h
+++ b/src/amd/vulkan/radv_pipeline_graphics.h
@@ -541,7 +541,7 @@ bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline);
 void radv_blend_remove_dst(VkBlendOp *func, VkBlendFactor *src_factor, VkBlendFactor *dst_factor,
                            VkBlendFactor expected_dst, VkBlendFactor replacement_src);
 
-unsigned radv_compact_spi_shader_col_format(const struct radv_shader *ps, uint32_t spi_shader_col_format);
+unsigned radv_compact_spi_shader_col_format(uint32_t spi_shader_col_format);
 
 unsigned radv_format_meta_fs_key(struct radv_device *device, VkFormat format);