asahi: track batches with incoherent writes

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27616>

src/gallium/drivers/asahi/agx_batch.c

@@ -132,6 +132,7 @@ agx_batch_init(struct agx_context *ctx,
    batch->geometry_state = 0;
    batch->initialized = false;
    batch->draws = 0;
+   batch->incoherent_writes = false;
    agx_bo_unreference(batch->sampler_heap.bo);
    batch->sampler_heap.bo = NULL;
    batch->sampler_heap.count = 0;

src/gallium/drivers/asahi/agx_pipe.c

@@ -664,6 +664,8 @@ agx_batch_track_image(struct agx_batch *batch, struct pipe_image_view *image)
    struct agx_resource *rsrc = agx_resource(image->resource);
 
    if (image->shader_access & PIPE_IMAGE_ACCESS_WRITE) {
+      batch->incoherent_writes = true;
+
       if (rsrc->base.target == PIPE_BUFFER) {
          agx_batch_writes_range(batch, rsrc, image->u.buf.offset,
                                 image->u.buf.size);

src/gallium/drivers/asahi/agx_state.c

@@ -4122,6 +4122,7 @@ agx_batch_geometry_params(struct agx_batch *batch, uint64_t input_index_buffer,
       if (rsrc) {
          params.xfb_offs_ptrs[i] = rsrc->bo->ptr.gpu;
          agx_batch_writes(batch, rsrc, 0);
+         batch->incoherent_writes = true;
       } else {
          params.xfb_offs_ptrs[i] = 0;
       }
@@ -4722,6 +4723,7 @@ agx_draw_patches(struct agx_context *ctx, const struct pipe_draw_info *info,
    heap_water += ALIGN(unrolled_patch_count * tcs->tess.output_stride, 4);
 
    agx_batch_writes(batch, agx_resource(heap), 0);
+   batch->incoherent_writes = true;
 
    uint64_t ib = 0;
    size_t ib_extent = 0;
@@ -5274,6 +5276,7 @@ agx_launch(struct agx_batch *batch, const struct pipe_grid_info *info,
 
       struct agx_resource *buffer = agx_resource(*res);
       agx_batch_writes(batch, buffer, 0);
+      batch->incoherent_writes = true;
    }
 
    agx_batch_add_bo(batch, cs->bo);

src/gallium/drivers/asahi/agx_state.h

@@ -360,6 +360,11 @@ struct agx_batch {
       unsigned bit_count;
    } bo_list;
 
+   /* If true, this batch contains a shader with a potentially incoherent write
+    * (e.g. image_write), needing a barrier later to access.
+    */
+   bool incoherent_writes;
+
    struct agx_pool pool, pipeline_pool;
 
    /* We may enqueue both CDM and VDM work, possibly to the same batch for

src/gallium/drivers/asahi/agx_uniforms.c

@@ -166,6 +166,7 @@ agx_set_ssbo_uniforms(struct agx_batch *batch, enum pipe_shader_type stage)
          if (st->ssbo_writable_mask & BITFIELD_BIT(cb)) {
             agx_batch_writes_range(batch, rsrc, sb->buffer_offset,
                                    sb->buffer_size);
+            batch->incoherent_writes = true;
          } else {
             agx_batch_reads(batch, rsrc);
          }