diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
index a2366f770fb..c0f3f0f2a33 100644
--- a/src/freedreno/common/freedreno_devices.py
+++ b/src/freedreno/common/freedreno_devices.py
@@ -1485,12 +1485,12 @@ add_gpus([
 # programming moves into the kernel, and what remains
 # should be easier to share between devices
 a8xx_gen2_raw_magic_regs = [
-        [A6XXRegs.REG_A8XX_GRAS_UNKNOWN_8228, 0x00000000],
-        [A6XXRegs.REG_A8XX_GRAS_UNKNOWN_8229, 0x00000000],
-        [A6XXRegs.REG_A8XX_GRAS_UNKNOWN_822A, 0x00000000],
-        [A6XXRegs.REG_A8XX_GRAS_UNKNOWN_822B, 0x00000000],
-        [A6XXRegs.REG_A8XX_GRAS_UNKNOWN_822C, 0x00000000],
-        [A6XXRegs.REG_A8XX_GRAS_UNKNOWN_822D, 0x00000000],
+        [A6XXRegs.REG_A8XX_GRAS_BIN_FOVEAT_XY_FDM_OFFSET + 0, 0x00000000],
+        [A6XXRegs.REG_A8XX_GRAS_BIN_FOVEAT_XY_FDM_OFFSET + 1, 0x00000000],
+        [A6XXRegs.REG_A8XX_GRAS_BIN_FOVEAT_XY_FDM_OFFSET + 2, 0x00000000],
+        [A6XXRegs.REG_A8XX_GRAS_BIN_FOVEAT_XY_FDM_OFFSET + 3, 0x00000000],
+        [A6XXRegs.REG_A8XX_GRAS_BIN_FOVEAT_XY_FDM_OFFSET + 4, 0x00000000],
+        [A6XXRegs.REG_A8XX_GRAS_BIN_FOVEAT_XY_FDM_OFFSET + 5, 0x00000000],
 
         [A6XXRegs.REG_A6XX_RB_UNKNOWN_8818,   0x00000000],
         [A6XXRegs.REG_A6XX_RB_UNKNOWN_8819,   0x00000000],
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index b939081b358..90d428064d5 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -1442,13 +1442,6 @@ by a particular renderpass/blit.
 	<reg32 offset="0x8203" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A8XX" />
 	<reg32 offset="0x8204" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit" variants="A8XX" />
 
-	<reg32 offset="0x8228" name="GRAS_UNKNOWN_8228" variants="A8XX-"/>
-	<reg32 offset="0x8229" name="GRAS_UNKNOWN_8229" variants="A8XX-"/>
-	<reg32 offset="0x822a" name="GRAS_UNKNOWN_822A" variants="A8XX-"/>
-	<reg32 offset="0x822b" name="GRAS_UNKNOWN_822B" variants="A8XX-"/>
-	<reg32 offset="0x822c" name="GRAS_UNKNOWN_822C" variants="A8XX-"/>
-	<reg32 offset="0x822d" name="GRAS_UNKNOWN_822D" variants="A8XX-"/>
-
 	<bitset name="a6xx_gras_cl_interp_cntl" inline="yes">
 		<!-- see also RB_INTERP_CNTL -->
 		<bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
@@ -1498,27 +1491,40 @@ by a particular renderpass/blit.
 	<reg32 offset="0x8008" name="GRAS_BIN_FOVEAT" type="a6xx_gras_bin_foveat" variants="A7XX" usage="cmd"/>
 	<reg32 offset="0x8206" name="GRAS_BIN_FOVEAT" type="a6xx_gras_bin_foveat" variants="A8XX-" usage="cmd"/>
 
-	<reg32 offset="0x8009" name="GRAS_BIN_FOVEAT_OFFSET_0" variants="A7XX-" usage="cmd">
+	<reg32 offset="0x8009" name="GRAS_BIN_FOVEAT_OFFSET_0" variants="A7XX" usage="cmd">
 		<bitfield name="XOFFSET_0" low="0" high="9" shr="2" type="uint"/>
 		<bitfield name="XOFFSET_1" low="10" high="19" shr="2" type="uint"/>
 		<bitfield name="XOFFSET_2" low="20" high="29" shr="2" type="uint"/>
 	</reg32>
-	<reg32 offset="0x800a" name="GRAS_BIN_FOVEAT_OFFSET_1" variants="A7XX-" usage="cmd">
+	<reg32 offset="0x800a" name="GRAS_BIN_FOVEAT_OFFSET_1" variants="A7XX" usage="cmd">
 		<bitfield name="XOFFSET_3" low="0" high="9" shr="2" type="uint"/>
 		<bitfield name="XOFFSET_4" low="10" high="19" shr="2" type="uint"/>
 		<bitfield name="XOFFSET_5" low="20" high="29" shr="2" type="uint"/>
 	</reg32>
-	<reg32 offset="0x800b" name="GRAS_BIN_FOVEAT_OFFSET_2" variants="A7XX-" usage="cmd">
+	<reg32 offset="0x800b" name="GRAS_BIN_FOVEAT_OFFSET_2" variants="A7XX" usage="cmd">
 		<bitfield name="YOFFSET_0" low="0" high="9" shr="2" type="uint"/>
 		<bitfield name="YOFFSET_1" low="10" high="19" shr="2" type="uint"/>
 		<bitfield name="YOFFSET_2" low="20" high="29" shr="2" type="uint"/>
 	</reg32>
-	<reg32 offset="0x800c" name="GRAS_BIN_FOVEAT_OFFSET_3" variants="A7XX-" usage="cmd">
+	<reg32 offset="0x800c" name="GRAS_BIN_FOVEAT_OFFSET_3" variants="A7XX" usage="cmd">
 		<bitfield name="YOFFSET_3" low="0" high="9" shr="2" type="uint"/>
 		<bitfield name="YOFFSET_4" low="10" high="19" shr="2" type="uint"/>
 		<bitfield name="YOFFSET_5" low="20" high="29" shr="2" type="uint"/>
 	</reg32>
 
+	<bitset name="a8xx_bin_foveat_xy" inline="yes">
+		<bitfield name="XOFFSET" low="0" high="13" type="uint"/>
+		<bitfield name="YOFFSET" low="16" high="29" type="uint"/>
+	</bitset>
+
+	<array offset="0x8220" name="GRAS_BIN_FOVEAT_XY" stride="1" length="6" variants="A8XX-" usage="cmd">
+		<reg32 offset="0" name="OFFSET" type="a8xx_bin_foveat_xy"/>
+	</array>
+
+	<array offset="0x8228" name="GRAS_BIN_FOVEAT_XY_FDM" stride="1" length="6" variants="A8XX-" usage="cmd">
+		<reg32 offset="0" name="OFFSET" type="a8xx_bin_foveat_xy"/>
+	</array>
+
 	<!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> -->
 
 	<!-- 0x8006-0x800f invalid -->
@@ -1877,6 +1883,29 @@ by a particular renderpass/blit.
 		<reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
 	</array>
 
+	<reg32 offset="0x829f" name="GRAS_SC_WINDOW_INV_SCISSOR_CNTL" variants="A8XX-">
+		<bitfield name="INCLUSION" pos="0" type="boolean"/> <!-- if not set, EXCLUSION -->
+		<bitfield name="VP0_INV_SCISSOR_0_EN" pos="4" type="boolean"/>
+		<bitfield name="VP0_INV_SCISSOR_1_EN" pos="5" type="boolean"/>
+		<bitfield name="VP1_INV_SCISSOR_0_EN" pos="6" type="boolean"/>
+		<bitfield name="VP1_INV_SCISSOR_1_EN" pos="7" type="boolean"/>
+		<bitfield name="VP2_INV_SCISSOR_0_EN" pos="8" type="boolean"/>
+		<bitfield name="VP2_INV_SCISSOR_1_EN" pos="9" type="boolean"/>
+		<bitfield name="VP3_INV_SCISSOR_0_EN" pos="10" type="boolean"/>
+		<bitfield name="VP3_INV_SCISSOR_1_EN" pos="11" type="boolean"/>
+		<bitfield name="VP4_INV_SCISSOR_0_EN" pos="12" type="boolean"/>
+		<bitfield name="VP4_INV_SCISSOR_1_EN" pos="13" type="boolean"/>
+		<bitfield name="VP5_INV_SCISSOR_0_EN" pos="14" type="boolean"/>
+		<bitfield name="VP5_INV_SCISSOR_1_EN" pos="15" type="boolean"/>
+	</reg32>
+
+	<array offset="0x82a0" name="GRAS_SC_WINDOW_VP" stride="4" length="6" variants="A8XX-">
+		<reg32 offset="0" name="INV_SCISSOR_0_TL" type="a6xx_scissor_xy"/>
+		<reg32 offset="1" name="INV_SCISSOR_0_BR" type="a6xx_scissor_xy"/>
+		<reg32 offset="2" name="INV_SCISSOR_1_TL" type="a6xx_scissor_xy"/>
+		<reg32 offset="3" name="INV_SCISSOR_1_BR" type="a6xx_scissor_xy"/>
+	</array>
+
 	<reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/>
 	<reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/>
 
@@ -2653,6 +2682,15 @@ by a particular renderpass/blit.
 	<reg32 offset="0x88f5" name="RB_BIN_FOVEAT" variants="A7XX-" usage="cmd">
 		<bitfield name="BINSCALEEN" pos="6" type="boolean"/>
 	</reg32>
+
+	<array offset="0x8950" name="RB_BIN_FOVEAT_XY" stride="1" length="6" variants="A8XX-" usage="cmd">
+		<reg32 offset="0" name="OFFSET" type="a8xx_bin_foveat_xy"/>
+	</array>
+
+	<array offset="0x8960" name="RB_BIN_FOVEAT_XY_FDM" stride="1" length="6" variants="A8XX-" usage="cmd">
+		<reg32 offset="0" name="OFFSET" type="a8xx_bin_foveat_xy"/>
+	</array>
+
 	<!-- 0x88f6-0x88ff invalid -->
 	<reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>
 	<reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH" usage="rp_blit">