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i965/vec4: Convert src_reg/dst_reg to brw_reg at the end of the visitor.

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This patch makes the visitor convert registers to the HW_REG file at the
very end, after register allocation, post-RA scheduling, and dependency
control flagging.  After that, everything is in fixed brw_regs.

This simplifies the code generator, as it can just use the hardware
registers rather than having to interpret our abstract files.  In
particular, interpreting the UNIFORM file meant reading prog_data
to figure out where push constants are supposed to start.

Having the part of the code that performs register allocation also
translate everything to hardware registers seems sensible.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Kenneth Graunke 2015-10-22 16:04:15 -07:00
parent f75f21a24a
commit 73ff0ead36
4 changed files with 92 additions and 110 deletions
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3
src/mesa/drivers/dri/i965/brw_ir_vec4.h
View file

@ -161,9 +161,6 @@ public:
const src_reg &src1 = src_reg(),
const src_reg &src2 = src_reg());
struct brw_reg get_dst(unsigned gen);
struct brw_reg get_src(const struct brw_vue_prog_data *prog_data, int i);
dst_reg dst;
src_reg src[3];

86
src/mesa/drivers/dri/i965/brw_vec4.cpp
View file

@ -1795,6 +1795,90 @@ vec4_visitor::emit_shader_time_write(int shader_time_subindex, src_reg value)
inst->mlen = 2;
}
void
vec4_visitor::convert_to_hw_regs()
{
foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
for (int i = 0; i < 3; i++) {
struct src_reg &src = inst->src[i];
struct brw_reg reg;
switch (src.file) {
case GRF:
reg = brw_vec8_grf(src.reg + src.reg_offset, 0);
reg.type = src.type;
reg.dw1.bits.swizzle = src.swizzle;
reg.abs = src.abs;
reg.negate = src.negate;
break;
case IMM:
reg = brw_imm_reg(src.type);
reg.dw1.ud = src.fixed_hw_reg.dw1.ud;
break;
case UNIFORM:
reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
(src.reg + src.reg_offset) / 2,
((src.reg + src.reg_offset) % 2) * 4),
0, 4, 1);
reg.type = src.type;
reg.dw1.bits.swizzle = src.swizzle;
reg.abs = src.abs;
reg.negate = src.negate;
/* This should have been moved to pull constants. */
assert(!src.reladdr);
break;
case HW_REG:
assert(src.type == src.fixed_hw_reg.type);
continue;
case BAD_FILE:
/* Probably unused. */
reg = brw_null_reg();
break;
default:
unreachable("not reached");
}
src.fixed_hw_reg = reg;
}
dst_reg &dst = inst->dst;
struct brw_reg reg;
switch (inst->dst.file) {
case GRF:
reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
reg.type = dst.type;
reg.dw1.bits.writemask = dst.writemask;
break;
case MRF:
assert(((dst.reg + dst.reg_offset) & ~(1 << 7)) < BRW_MAX_MRF(devinfo->gen));
reg = brw_message_reg(dst.reg + dst.reg_offset);
reg.type = dst.type;
reg.dw1.bits.writemask = dst.writemask;
break;
case HW_REG:
assert(dst.type == dst.fixed_hw_reg.type);
reg = dst.fixed_hw_reg;
break;
case BAD_FILE:
reg = brw_null_reg();
break;
default:
unreachable("not reached");
}
dst.fixed_hw_reg = reg;
}
}
bool
vec4_visitor::run()
{
@ -1916,6 +2000,8 @@ vec4_visitor::run()
opt_set_dependency_control();
convert_to_hw_regs();
if (last_scratch > 0) {
prog_data->base.total_scratch =
brw_get_scratch_size(last_scratch * REG_SIZE);

1
src/mesa/drivers/dri/i965/brw_vec4.h
View file

@ -159,6 +159,7 @@ public:
bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
void opt_set_dependency_control();
void opt_schedule_instructions();
void convert_to_hw_regs();
vec4_instruction *emit(vec4_instruction *inst);

112
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
View file

@ -34,108 +34,6 @@ extern "C" {
namespace brw {
struct brw_reg
vec4_instruction::get_dst(unsigned gen)
{
struct brw_reg brw_reg;
switch (dst.file) {
case GRF:
brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
brw_reg = retype(brw_reg, dst.type);
brw_reg.dw1.bits.writemask = dst.writemask;
break;
case MRF:
assert(((dst.reg + dst.reg_offset) & ~(1 << 7)) < BRW_MAX_MRF(gen));
brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
brw_reg = retype(brw_reg, dst.type);
brw_reg.dw1.bits.writemask = dst.writemask;
break;
case HW_REG:
assert(dst.type == dst.fixed_hw_reg.type);
brw_reg = dst.fixed_hw_reg;
break;
case BAD_FILE:
brw_reg = brw_null_reg();
break;
default:
unreachable("not reached");
}
return brw_reg;
}
struct brw_reg
vec4_instruction::get_src(const struct brw_vue_prog_data *prog_data, int i)
{
struct brw_reg brw_reg;
switch (src[i].file) {
case GRF:
brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
brw_reg = retype(brw_reg, src[i].type);
brw_reg.dw1.bits.swizzle = src[i].swizzle;
if (src[i].abs)
brw_reg = brw_abs(brw_reg);
if (src[i].negate)
brw_reg = negate(brw_reg);
break;
case IMM:
switch (src[i].type) {
case BRW_REGISTER_TYPE_F:
brw_reg = brw_imm_f(src[i].fixed_hw_reg.dw1.f);
break;
case BRW_REGISTER_TYPE_D:
brw_reg = brw_imm_d(src[i].fixed_hw_reg.dw1.d);
break;
case BRW_REGISTER_TYPE_UD:
brw_reg = brw_imm_ud(src[i].fixed_hw_reg.dw1.ud);
break;
case BRW_REGISTER_TYPE_VF:
brw_reg = brw_imm_vf(src[i].fixed_hw_reg.dw1.ud);
break;
default:
unreachable("not reached");
}
break;
case UNIFORM:
brw_reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
(src[i].reg + src[i].reg_offset) / 2,
((src[i].reg + src[i].reg_offset) % 2) * 4),
0, 4, 1);
brw_reg = retype(brw_reg, src[i].type);
brw_reg.dw1.bits.swizzle = src[i].swizzle;
if (src[i].abs)
brw_reg = brw_abs(brw_reg);
if (src[i].negate)
brw_reg = negate(brw_reg);
/* This should have been moved to pull constants. */
assert(!src[i].reladdr);
break;
case HW_REG:
assert(src[i].type == src[i].fixed_hw_reg.type);
brw_reg = src[i].fixed_hw_reg;
break;
case BAD_FILE:
/* Probably unused. */
brw_reg = brw_null_reg();
break;
case ATTR:
default:
unreachable("not reached");
}
return brw_reg;
}
vec4_generator::vec4_generator(const struct brw_compiler *compiler,
void *log_data,
struct brw_vue_prog_data *prog_data,
@ -476,7 +374,7 @@ vec4_generator::generate_gs_urb_write_allocate(vec4_instruction *inst)
/* We pass the temporary passed in src0 as the writeback register */
brw_urb_WRITE(p,
inst->get_src(this->prog_data, 0), /* dest */
inst->src[0].fixed_hw_reg, /* dest */
inst->base_mrf, /* starting mrf reg nr */
src,
BRW_URB_WRITE_ALLOCATE_COMPLETE,
@ -489,8 +387,8 @@ vec4_generator::generate_gs_urb_write_allocate(vec4_instruction *inst)
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_MOV(p, get_element_ud(inst->get_dst(devinfo->gen), 0),
get_element_ud(inst->get_src(this->prog_data, 0), 0));
brw_MOV(p, get_element_ud(inst->dst.fixed_hw_reg, 0),
get_element_ud(inst->src[0].fixed_hw_reg, 0));
brw_set_default_access_mode(p, BRW_ALIGN_16);
brw_pop_insn_state(p);
}
@ -1154,9 +1052,9 @@ vec4_generator::generate_code(const cfg_t *cfg, const nir_shader *nir)
annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
for (unsigned int i = 0; i < 3; i++) {
src[i] = inst->get_src(this->prog_data, i);
src[i] = inst->src[i].fixed_hw_reg;
}
dst = inst->get_dst(devinfo->gen);
dst = inst->dst.fixed_hw_reg;
brw_set_default_predicate_control(p, inst->predicate);
brw_set_default_predicate_inverse(p, inst->predicate_inverse);