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iris: Pick scanout PAT entry for scanout buffers

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Scanout PAT was never being picked what could cause render cache to
not be flushed during page flips causing visual corruption on
displays.

Cc: stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33127>
This commit is contained in:
José Roberto de Souza 2025-01-15 12:44:18 -08:00 • committed by Marge Bot
parent 572eacec9e
commit 73f3de12ef
4 changed files with 25 additions and 5 deletions
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3
src/gallium/drivers/iris/i915/iris_kmd_backend.c
View file

@ -123,7 +123,8 @@ i915_gem_create(struct iris_bufmgr *bufmgr,
/* Set PAT param */
struct drm_i915_gem_create_ext_set_pat set_pat_param = { 0 };
if (devinfo->has_set_pat_uapi) {
set_pat_param.pat_index = iris_heap_to_pat_entry(devinfo, heap)->index;
set_pat_param.pat_index = iris_heap_to_pat_entry(devinfo, heap,
alloc_flags & BO_ALLOC_SCANOUT)->index;
intel_i915_gem_add_ext(&create.extensions,
I915_GEM_CREATE_EXT_SET_PAT,
&set_pat_param.base);

11
src/gallium/drivers/iris/iris_bufmgr.c
View file

@ -1160,6 +1160,7 @@ alloc_fresh_bo(struct iris_bufmgr *bufmgr, uint64_t bo_size, unsigned flags)
bo->idle = true;
bo->zeroed = true;
bo->real.capture = (flags & BO_ALLOC_CAPTURE) != 0;
bo->real.scanout = (flags & BO_ALLOC_SCANOUT) != 0;
return bo;
}
@ -2654,8 +2655,16 @@ iris_bufmgr_compute_engine_supported(struct iris_bufmgr *bufmgr)
*/
const struct intel_device_info_pat_entry *
iris_heap_to_pat_entry(const struct intel_device_info *devinfo,
enum iris_heap heap)
enum iris_heap heap, bool scanout)
{
if (scanout) {
if (iris_heap_is_compressed(heap) == false)
return &devinfo->pat.scanout;
WARN_ONCE(iris_heap_is_compressed(heap),
"update heap_to_pat_entry when compressed scanout pat entries are added");
}
switch (heap) {
case IRIS_HEAP_SYSTEM_MEMORY_CACHED_COHERENT:
return &devinfo->pat.cached_coherent;

12
src/gallium/drivers/iris/iris_bufmgr.h
View file

@ -215,6 +215,13 @@ iris_heap_is_device_local(enum iris_heap heap)
heap == IRIS_HEAP_DEVICE_LOCAL_COMPRESSED;
}
static inline bool
iris_heap_is_compressed(enum iris_heap heap)
{
return heap == IRIS_HEAP_SYSTEM_MEMORY_UNCACHED_COMPRESSED ||
heap == IRIS_HEAP_DEVICE_LOCAL_COMPRESSED;
}
#define IRIS_BATCH_COUNT 3
struct iris_bo_screen_deps {
@ -349,6 +356,9 @@ struct iris_bo {
* this set before batch_submit().
*/
bool capture;
/** Boolean of whether this buffer can be scanout to display */
bool scanout;
} real;
struct {
struct pb_slab_entry entry;
@ -620,7 +630,7 @@ iris_bo_bump_seqno(struct iris_bo *bo, uint64_t seqno,
*/
const struct intel_device_info_pat_entry *
iris_heap_to_pat_entry(const struct intel_device_info *devinfo,
enum iris_heap heap);
enum iris_heap heap, bool scanout);
enum iris_memory_zone iris_memzone_for_address(uint64_t address);

4
src/gallium/drivers/iris/xe/iris_kmd_backend.c
View file

@ -69,7 +69,7 @@ xe_gem_create(struct iris_bufmgr *bufmgr,
const struct intel_device_info *devinfo = iris_bufmgr_get_device_info(bufmgr);
const struct intel_device_info_pat_entry *pat_entry;
pat_entry = iris_heap_to_pat_entry(devinfo, heap_flags);
pat_entry = iris_heap_to_pat_entry(devinfo, heap_flags, alloc_flags & BO_ALLOC_SCANOUT);
switch (pat_entry->mmap) {
case INTEL_DEVICE_INFO_MMAP_MODE_WC:
gem_create.cpu_caching = DRM_XE_GEM_CPU_CACHING_WC;
@ -146,7 +146,7 @@ xe_gem_vm_bind_op(struct iris_bo *bo, uint32_t op)
.bind.range = range,
.bind.addr = intel_48b_address(bo->address),
.bind.op = op,
.bind.pat_index = iris_heap_to_pat_entry(devinfo, bo->real.heap)->index,
.bind.pat_index = iris_heap_to_pat_entry(devinfo, bo->real.heap, bo->real.scanout)->index,
.bind.flags = flags,
};