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nv50: expose images/buffers/compute

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This is not enough for desktop GL, since that requires support for
images/buffers in fragment shaders. However this is sufficient for ES
3.1's compute needs, where images/buffers need only be supported in
compute shaders.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10569>
This commit is contained in:
Ilia Mirkin 2021-02-24 22:38:10 -05:00
parent 503d97445a
commit 73a49c84d7
1 changed files with 13 additions and 9 deletions
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22
src/gallium/drivers/nouveau/nv50/nv50_screen.c
View file

@ -133,6 +133,8 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return 8;
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
return 1;
case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
return NV50_MAX_GLOBALS - 1;
case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
return 8;
@ -150,7 +152,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_GS_INVOCATIONS:
return 0;
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
return 0;
return 1 << 27;
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
return 2048;
case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
@ -159,6 +161,8 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return 256;
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
return 16; /* 256 for binding as RT, but that's not possible in GL */
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
return 256; /* the access limit is aligned to 256 */
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
case PIPE_CAP_MAX_VIEWPORTS:
@ -253,6 +257,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_PACKED_STREAM_OUTPUT:
case PIPE_CAP_CLEAR_SCISSORED:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
case PIPE_CAP_COMPUTE:
return 1;
case PIPE_CAP_SEAMLESS_CUBE_MAP:
return 1; /* class_3d >= NVA0_3D_CLASS; */
@ -295,7 +300,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_GENERATE_MIPMAP:
case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
@ -329,7 +333,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_LOAD_CONSTBUF:
case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
case PIPE_CAP_TILE_RASTER_ORDER:
case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
case PIPE_CAP_CONTEXT_PRIORITY_MASK:
@ -352,7 +355,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
case PIPE_CAP_NIR_COMPACT_ARRAYS:
case PIPE_CAP_COMPUTE:
case PIPE_CAP_IMAGE_LOAD_FORMATTED:
case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
@ -428,8 +430,8 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
case PIPE_SHADER_FRAGMENT:
break;
case PIPE_SHADER_COMPUTE:
break;
default:
return 0;
}
@ -480,6 +482,10 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
/* The chip could handle more sampler views than samplers */
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return MIN2(16, PIPE_MAX_SAMPLERS);
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
case PIPE_SHADER_CAP_PREFERRED_IR:
return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
@ -491,8 +497,6 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
@ -542,9 +546,9 @@ nv50_screen_get_compute_param(struct pipe_screen *pscreen,
switch (param) {
case PIPE_COMPUTE_CAP_GRID_DIMENSION:
RET((uint64_t []) { 2 });
RET((uint64_t []) { 3 });
case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
RET(((uint64_t []) { 65535, 65535 }));
RET(((uint64_t []) { 65535, 65535, 65535 }));
case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
RET(((uint64_t []) { 512, 512, 64 }));
case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: