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freedreno, turnip: set correct reg_size_vec4 for a6xx_gen1_low

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Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20991>
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Amber 2023-04-10 13:49:54 +02:00 • committed by Marge Bot
parent 49ed69369e
commit 7373ab7f95
1 changed files with 1 additions and 0 deletions
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src/freedreno/common/freedreno_devices.py
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@ -256,6 +256,7 @@ a6xx_gen1 = dict(
# a605, a608, a610, 612
a6xx_gen1_low = {**a6xx_gen1, **dict(
has_gmem_fast_clear = False,
reg_size_vec4 = 48,
has_hw_multiview = False,
has_sampler_minmax = False,
has_fs_tex_prefetch = False,