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https://gitlab.freedesktop.org/mesa/mesa.git
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radeonsi/uvd_enc: Support raw packed headers
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32829>
This commit is contained in:
David Rosca
Marge Bot
parent
da9de889aa
commit
73657d4246
3 changed files with 134 additions and 46 deletions
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@ -23,8 +23,6 @@ static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
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enc->enc_pic.desc = pic;
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enc->enc_pic.picture_type = pic->picture_type;
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enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
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enc->enc_pic.is_iframe = (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR) ||
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(pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_I);
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enc->enc_pic.enc_params.reference_picture_index =
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pic->ref_list0[0] == PIPE_H2645_LIST_REF_INVALID_ENTRY ? 0xffffffff : pic->ref_list0[0];
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enc->enc_pic.enc_params.reconstructed_picture_index = pic->dpb_curr_pic;
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@ -187,6 +185,79 @@ static void radeon_uvd_enc_begin_frame(struct pipe_video_codec *encoder,
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}
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}
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static void *radeon_uvd_enc_encode_headers(struct radeon_uvd_encoder *enc)
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{
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unsigned num_slices = 0, num_headers = 0;
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util_dynarray_foreach(&enc->enc_pic.desc->raw_headers, struct pipe_enc_raw_header, header) {
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if (header->is_slice)
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num_slices++;
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num_headers++;
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}
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if (!num_headers || !num_slices || num_headers == num_slices)
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return NULL;
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size_t segments_size =
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sizeof(struct ruvd_enc_output_unit_segment) * (num_headers - num_slices + 1);
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struct ruvd_enc_feedback_data *data =
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CALLOC_VARIANT_LENGTH_STRUCT(ruvd_enc_feedback_data, segments_size);
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if (!data)
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return NULL;
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uint8_t *ptr = enc->ws->buffer_map(enc->ws, enc->bs_handle, &enc->cs,
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PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
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if (!ptr) {
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RVID_ERR("Can't map bs buffer.\n");
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FREE(data);
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return NULL;
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}
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unsigned offset = 0;
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struct ruvd_enc_output_unit_segment *slice_segment = NULL;
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util_dynarray_foreach(&enc->enc_pic.desc->raw_headers, struct pipe_enc_raw_header, header) {
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if (header->is_slice) {
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if (slice_segment)
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continue;
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slice_segment = &data->segments[data->num_segments];
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slice_segment->is_slice = true;
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} else {
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unsigned size;
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switch (header->type) {
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case PIPE_H265_NAL_VPS:
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size = radeon_uvd_enc_write_vps(enc, ptr + offset);
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break;
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case PIPE_H265_NAL_SPS:
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size = radeon_uvd_enc_write_sps(enc, ptr + offset);
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break;
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case PIPE_H265_NAL_PPS:
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size = radeon_uvd_enc_write_pps(enc, ptr + offset);
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break;
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default:
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assert(header->buffer);
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memcpy(ptr + offset, header->buffer, header->size);
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size = header->size;
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break;
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}
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data->segments[data->num_segments].size = size;
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data->segments[data->num_segments].offset = offset;
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offset += size;
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}
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data->num_segments++;
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}
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enc->bs_offset = align(offset, 16);
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assert(enc->bs_offset < enc->bs_size);
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assert(slice_segment);
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slice_segment->offset = enc->bs_offset;
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enc->ws->buffer_unmap(enc->ws, enc->bs_handle);
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return data;
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}
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static void radeon_uvd_enc_encode_bitstream(struct pipe_video_codec *encoder,
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struct pipe_video_buffer *source,
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struct pipe_resource *destination, void **fb)
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@ -194,6 +265,7 @@ static void radeon_uvd_enc_encode_bitstream(struct pipe_video_codec *encoder,
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struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
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enc->get_buffer(destination, &enc->bs_handle, NULL);
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enc->bs_size = destination->width0;
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enc->bs_offset = 0;
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*fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
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@ -202,6 +274,8 @@ static void radeon_uvd_enc_encode_bitstream(struct pipe_video_codec *encoder,
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return;
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}
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enc->fb->user_data = radeon_uvd_enc_encode_headers(enc);
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enc->need_feedback = true;
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enc->encode(enc);
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}
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@ -244,15 +318,38 @@ static void radeon_uvd_enc_get_feedback(struct pipe_video_codec *encoder, void *
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struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *)encoder;
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struct rvid_buffer *fb = feedback;
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if (NULL != size) {
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radeon_uvd_enc_feedback_t *fb_data = (radeon_uvd_enc_feedback_t *)enc->ws->buffer_map(
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enc->ws, fb->res->buf, &enc->cs, PIPE_MAP_READ_WRITE | RADEON_MAP_TEMPORARY);
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radeon_uvd_enc_feedback_t *fb_data = (radeon_uvd_enc_feedback_t *)enc->ws->buffer_map(
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enc->ws, fb->res->buf, &enc->cs, PIPE_MAP_READ_WRITE | RADEON_MAP_TEMPORARY);
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if (!fb_data->status)
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*size = fb_data->bitstream_size;
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else
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*size = 0;
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enc->ws->buffer_unmap(enc->ws, fb->res->buf);
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if (!fb_data->status)
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*size = fb_data->bitstream_size;
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else
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*size = 0;
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enc->ws->buffer_unmap(enc->ws, fb->res->buf);
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metadata->present_metadata = PIPE_VIDEO_FEEDBACK_METADATA_TYPE_CODEC_UNIT_LOCATION;
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if (fb->user_data) {
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struct ruvd_enc_feedback_data *data = fb->user_data;
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metadata->codec_unit_metadata_count = data->num_segments;
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for (unsigned i = 0; i < data->num_segments; i++) {
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metadata->codec_unit_metadata[i].offset = data->segments[i].offset;
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if (data->segments[i].is_slice) {
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metadata->codec_unit_metadata[i].size = *size;
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metadata->codec_unit_metadata[i].flags = 0;
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} else {
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metadata->codec_unit_metadata[i].size = data->segments[i].size;
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metadata->codec_unit_metadata[i].flags = PIPE_VIDEO_CODEC_UNIT_LOCATION_FLAG_SINGLE_NALU;
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}
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}
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FREE(fb->user_data);
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fb->user_data = NULL;
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} else {
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metadata->codec_unit_metadata_count = 1;
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metadata->codec_unit_metadata[0].offset = 0;
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metadata->codec_unit_metadata[0].size = *size;
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metadata->codec_unit_metadata[0].flags = 0;
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}
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si_vid_destroy_buffer(fb);
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@ -317,8 +317,6 @@ struct radeon_uvd_enc_pic {
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unsigned nal_unit_type;
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unsigned temporal_id;
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bool is_iframe;
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ruvd_enc_task_info_t task_info;
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ruvd_enc_session_init_t session_init;
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ruvd_enc_layer_control_t layer_ctrl;
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@ -359,6 +357,7 @@ struct radeon_uvd_encoder {
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struct pb_buffer_lean *bs_handle;
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unsigned bs_size;
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unsigned bs_offset;
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unsigned dpb_slots;
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@ -375,9 +374,24 @@ struct radeon_uvd_encoder {
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bool need_rc_per_pic;
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};
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struct ruvd_enc_output_unit_segment {
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bool is_slice;
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unsigned size;
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unsigned offset;
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};
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struct ruvd_enc_feedback_data {
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unsigned num_segments;
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struct ruvd_enc_output_unit_segment segments[];
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};
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struct si_screen;
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void radeon_uvd_enc_1_1_init(struct radeon_uvd_encoder *enc);
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bool si_radeon_uvd_enc_supported(struct si_screen *sscreen);
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unsigned int radeon_uvd_enc_write_vps(struct radeon_uvd_encoder *enc, uint8_t *out);
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unsigned int radeon_uvd_enc_write_sps(struct radeon_uvd_encoder *enc, uint8_t *out);
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unsigned int radeon_uvd_enc_write_pps(struct radeon_uvd_encoder *enc, uint8_t *out);
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#endif // _RADEON_UVD_ENC_H
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@ -277,17 +277,13 @@ static void radeon_uvd_enc_quality_params(struct radeon_uvd_encoder *enc)
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RADEON_ENC_END();
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}
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static void radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
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unsigned int radeon_uvd_enc_write_sps(struct radeon_uvd_encoder *enc, uint8_t *out)
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{
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struct radeon_bitstream bs;
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struct pipe_h265_enc_seq_param *sps = &enc->enc_pic.desc->seq;
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int i;
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RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
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RADEON_ENC_CS(RENC_UVD_NALU_TYPE_SPS);
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uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
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radeon_bs_reset(&bs, NULL, &enc->cs);
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radeon_bs_reset(&bs, out, NULL);
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radeon_bs_set_emulation_prevention(&bs, false);
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radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
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radeon_bs_code_fixed_bits(&bs, 0x4201, 16);
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@ -412,21 +408,15 @@ static void radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
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radeon_bs_code_fixed_bits(&bs, 0x1, 1);
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radeon_bs_byte_align(&bs);
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radeon_bs_flush_headers(&bs);
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*size_in_bytes = bs.bits_output / 8;
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RADEON_ENC_END();
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return bs.bits_output / 8;
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}
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static void radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder *enc)
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unsigned int radeon_uvd_enc_write_pps(struct radeon_uvd_encoder *enc, uint8_t *out)
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{
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struct radeon_bitstream bs;
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struct pipe_h265_enc_pic_param *pps = &enc->enc_pic.desc->pic;
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RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
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RADEON_ENC_CS(RENC_UVD_NALU_TYPE_PPS);
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uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
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radeon_bs_reset(&bs, NULL, &enc->cs);
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radeon_bs_reset(&bs, out, NULL);
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radeon_bs_set_emulation_prevention(&bs, false);
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radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
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radeon_bs_code_fixed_bits(&bs, 0x4401, 16);
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@ -473,22 +463,16 @@ static void radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder *enc)
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radeon_bs_code_fixed_bits(&bs, 0x1, 1);
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radeon_bs_byte_align(&bs);
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radeon_bs_flush_headers(&bs);
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*size_in_bytes = bs.bits_output / 8;
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RADEON_ENC_END();
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return bs.bits_output / 8;
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}
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static void radeon_uvd_enc_nalu_vps_hevc(struct radeon_uvd_encoder *enc)
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unsigned int radeon_uvd_enc_write_vps(struct radeon_uvd_encoder *enc, uint8_t *out)
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{
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struct radeon_bitstream bs;
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struct pipe_h265_enc_vid_param *vps = &enc->enc_pic.desc->vid;
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int i;
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RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_INSERT_NALU_BUFFER);
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RADEON_ENC_CS(RENC_UVD_NALU_TYPE_VPS);
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uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
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radeon_bs_reset(&bs, NULL, &enc->cs);
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radeon_bs_reset(&bs, out, NULL);
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radeon_bs_set_emulation_prevention(&bs, false);
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radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
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radeon_bs_code_fixed_bits(&bs, 0x4001, 16);
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@ -524,9 +508,7 @@ static void radeon_uvd_enc_nalu_vps_hevc(struct radeon_uvd_encoder *enc)
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radeon_bs_code_fixed_bits(&bs, 0x1, 1);
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radeon_bs_byte_align(&bs);
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radeon_bs_flush_headers(&bs);
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*size_in_bytes = bs.bits_output / 8;
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RADEON_ENC_END();
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return bs.bits_output / 8;
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}
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static void radeon_uvd_enc_slice_header_hevc(struct radeon_uvd_encoder *enc)
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@ -715,7 +697,7 @@ static void radeon_uvd_enc_bitstream(struct radeon_uvd_encoder *enc)
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{
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enc->enc_pic.bit_buf.mode = RENC_UVD_SWIZZLE_MODE_LINEAR;
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enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size;
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enc->enc_pic.bit_buf.video_bitstream_data_offset = 0;
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enc->enc_pic.bit_buf.video_bitstream_data_offset = enc->bs_offset;
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RADEON_ENC_BEGIN(RENC_UVD_IB_PARAM_VIDEO_BITSTREAM_BUFFER);
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RADEON_ENC_CS(enc->enc_pic.bit_buf.mode);
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@ -800,7 +782,7 @@ static void radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc)
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enc->enc_pic.enc_params.pic_type = RENC_UVD_PICTURE_TYPE_I;
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}
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enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size;
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enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size - enc->bs_offset;
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if (sscreen->info.gfx_level < GFX9) {
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enc->enc_pic.enc_params.input_pic_luma_pitch =
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(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe);
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@ -933,11 +915,6 @@ static void encode(struct radeon_uvd_encoder *enc)
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enc->enc_pic.layer_sel.temporal_layer_index = enc->enc_pic.temporal_id;
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radeon_uvd_enc_layer_select(enc);
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if (enc->enc_pic.is_iframe) {
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radeon_uvd_enc_nalu_vps_hevc(enc);
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radeon_uvd_enc_nalu_pps_hevc(enc);
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radeon_uvd_enc_nalu_sps_hevc(enc);
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}
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radeon_uvd_enc_slice_header_hevc(enc);
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radeon_uvd_enc_encode_params_hevc(enc);
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