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radeonsi/gfx10: enable GS fast launch for triangles and strips with NGG culling
Only non-indexed triangle lists and strips are supported. This increases performance if there is something to cull. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
This commit is contained in:
Marek Olšák
parent
c377f45c18
commit
735a3ba007
6 changed files with 221 additions and 53 deletions
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@ -667,6 +667,20 @@ static LLVMValueRef ngg_nogs_vertex_ptr(struct si_shader_context *ctx,
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return LLVMBuildGEP(ctx->ac.builder, tmp, &vtxid, 1, "");
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}
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static LLVMValueRef si_insert_input_v4i32(struct si_shader_context *ctx,
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LLVMValueRef ret, struct ac_arg param,
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unsigned return_index)
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{
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LLVMValueRef v = ac_get_arg(&ctx->ac, param);
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for (unsigned i = 0; i < 4; i++) {
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ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
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ac_llvm_extract_elem(&ctx->ac, v, i),
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return_index + i, "");
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}
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return ret;
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}
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static void load_bitmasks_2x64(struct si_shader_context *ctx,
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LLVMValueRef lds_ptr, unsigned dw_offset,
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LLVMValueRef mask[2], LLVMValueRef *total_bitcount)
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@ -874,10 +888,18 @@ void gfx10_emit_ngg_culling_epilogue_4x_wave32(struct ac_shader_abi *abi,
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* - In ES threads, update the ES input VGPRs (VertexID, InstanceID, TES inputs).
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*/
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LLVMValueRef vtxindex[] = {
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si_unpack_param(ctx, ctx->gs_vtx01_offset, 0, 16),
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si_unpack_param(ctx, ctx->gs_vtx01_offset, 16, 16),
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si_unpack_param(ctx, ctx->gs_vtx23_offset, 0, 16),
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LLVMValueRef vtxindex[3];
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if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL) {
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/* For the GS fast launch, the VS prologs simply puts the Vertex IDs
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* into these VGPRs.
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*/
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vtxindex[0] = ac_get_arg(&ctx->ac, ctx->gs_vtx01_offset);
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vtxindex[1] = ac_get_arg(&ctx->ac, ctx->gs_vtx23_offset);
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vtxindex[2] = ac_get_arg(&ctx->ac, ctx->gs_vtx45_offset);
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} else {
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vtxindex[0] = si_unpack_param(ctx, ctx->gs_vtx01_offset, 0, 16);
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vtxindex[1] = si_unpack_param(ctx, ctx->gs_vtx01_offset, 16, 16);
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vtxindex[2] = si_unpack_param(ctx, ctx->gs_vtx23_offset, 0, 16);
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};
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LLVMValueRef gs_vtxptr[] = {
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ngg_nogs_vertex_ptr(ctx, vtxindex[0]),
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@ -1143,6 +1165,11 @@ void gfx10_emit_ngg_culling_epilogue_4x_wave32(struct ac_shader_abi *abi,
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8 + SI_SGPR_DRAWID);
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ret = si_insert_input_ptr(ctx, ret, ctx->vertex_buffers,
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8 + SI_VS_NUM_USER_SGPR);
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for (unsigned i = 0; i < shader->selector->num_vbos_in_user_sgprs; i++) {
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ret = si_insert_input_v4i32(ctx, ret, ctx->vb_descriptors[i],
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8 + SI_SGPR_VS_VB_DESCRIPTOR_FIRST + i * 4);
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}
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} else {
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assert(ctx->type == PIPE_SHADER_TESS_EVAL);
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ret = si_insert_input_ptr(ctx, ret, ctx->tcs_offchip_layout,
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@ -1152,10 +1179,16 @@ void gfx10_emit_ngg_culling_epilogue_4x_wave32(struct ac_shader_abi *abi,
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}
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unsigned vgpr;
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if (ctx->type == PIPE_SHADER_VERTEX)
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vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR + 1;
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else
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if (ctx->type == PIPE_SHADER_VERTEX) {
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if (shader->selector->num_vbos_in_user_sgprs) {
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vgpr = 8 + SI_SGPR_VS_VB_DESCRIPTOR_FIRST +
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shader->selector->num_vbos_in_user_sgprs * 4;
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} else {
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vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR + 1;
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}
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} else {
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vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
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}
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val = LLVMBuildLoad(builder, new_vgpr0, "");
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ret = LLVMBuildInsertValue(builder, ret, ac_to_float(&ctx->ac, val),
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@ -1986,8 +2019,16 @@ void gfx10_ngg_calculate_subgroup_info(struct si_shader *shader)
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/* All these are per subgroup: */
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bool max_vert_out_per_gs_instance = false;
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unsigned max_esverts_base = 128;
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unsigned max_gsprims_base = 128; /* default prim group size clamp */
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unsigned max_esverts_base = 128;
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if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST) {
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max_gsprims_base = 128 / 3;
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max_esverts_base = max_gsprims_base * 3;
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} else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP) {
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max_gsprims_base = 126;
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max_esverts_base = 128;
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}
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/* Hardware has the following non-natural restrictions on the value
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* of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
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@ -802,7 +802,7 @@ union si_vgt_param_key {
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uint32_t index;
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};
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#define SI_NUM_VGT_STAGES_KEY_BITS 5
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#define SI_NUM_VGT_STAGES_KEY_BITS 6
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#define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
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/* The VGT_SHADER_STAGES key used to index the table of precomputed values.
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@ -813,6 +813,7 @@ union si_vgt_stages_key {
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#if UTIL_ARCH_LITTLE_ENDIAN
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unsigned tess:1;
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unsigned gs:1;
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unsigned ngg_gs_fast_launch:1;
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unsigned ngg_passthrough:1;
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unsigned ngg:1; /* gfx10+ */
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unsigned streamout:1; /* only used with NGG */
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@ -822,6 +823,7 @@ union si_vgt_stages_key {
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unsigned streamout:1;
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unsigned ngg:1;
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unsigned ngg_passthrough:1;
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unsigned ngg_gs_fast_launch:1;
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unsigned gs:1;
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unsigned tess:1;
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#endif
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@ -1474,11 +1474,20 @@ void si_create_function(struct si_shader_context *ctx, bool ngg_cull_shader)
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ctx->type == PIPE_SHADER_TESS_EVAL)) {
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unsigned num_user_sgprs, num_vgprs;
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/* For the NGG cull shader, add 1 SGPR to hold the vertex buffer pointer. */
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if (ctx->type == PIPE_SHADER_VERTEX)
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if (ctx->type == PIPE_SHADER_VERTEX) {
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/* For the NGG cull shader, add 1 SGPR to hold
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* the vertex buffer pointer.
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*/
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num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR + ngg_cull_shader;
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else
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if (ngg_cull_shader && shader->selector->num_vbos_in_user_sgprs) {
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assert(num_user_sgprs <= 8 + SI_SGPR_VS_VB_DESCRIPTOR_FIRST);
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num_user_sgprs = SI_SGPR_VS_VB_DESCRIPTOR_FIRST +
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shader->selector->num_vbos_in_user_sgprs * 4;
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}
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} else {
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num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
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}
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/* The NGG cull shader has to return all 9 VGPRs + the old thread ID.
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*
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@ -2278,13 +2287,16 @@ static void si_init_exec_from_input(struct si_shader_context *ctx,
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}
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static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
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const struct si_vs_prolog_bits *key)
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const struct si_vs_prolog_bits *prolog_key,
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const struct si_shader_key *key,
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bool ngg_cull_shader)
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{
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/* VGPR initialization fixup for Vega10 and Raven is always done in the
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* VS prolog. */
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return sel->vs_needs_prolog ||
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key->ls_vgpr_fix ||
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key->unpack_instance_id_from_vertex_id;
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prolog_key->ls_vgpr_fix ||
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prolog_key->unpack_instance_id_from_vertex_id ||
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(ngg_cull_shader && key->opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL);
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}
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static bool si_build_main_function(struct si_shader_context *ctx,
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@ -2436,7 +2448,8 @@ static bool si_build_main_function(struct si_shader_context *ctx,
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(shader->key.as_es || shader->key.as_ls) &&
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(ctx->type == PIPE_SHADER_TESS_EVAL ||
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(ctx->type == PIPE_SHADER_VERTEX &&
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!si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
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!si_vs_needs_prolog(sel, &shader->key.part.vs.prolog,
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&shader->key, ngg_cull_shader)))) {
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si_init_exec_from_input(ctx,
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ctx->merged_wave_info, 0);
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} else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
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@ -2551,8 +2564,14 @@ static void si_get_vs_prolog_key(const struct si_shader_info *info,
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key->vs_prolog.as_es = shader_out->key.as_es;
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key->vs_prolog.as_ngg = shader_out->key.as_ngg;
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if (!ngg_cull_shader)
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if (ngg_cull_shader) {
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key->vs_prolog.gs_fast_launch_tri_list = !!(shader_out->key.opt.ngg_culling &
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SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST);
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key->vs_prolog.gs_fast_launch_tri_strip = !!(shader_out->key.opt.ngg_culling &
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SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP);
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} else {
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key->vs_prolog.has_ngg_cull_inputs = !!shader_out->key.opt.ngg_culling;
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}
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if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
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key->vs_prolog.as_ls = 1;
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@ -2937,11 +2956,12 @@ int si_compile_shader(struct si_screen *sscreen,
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if (shader->is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
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LLVMValueRef parts[4];
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unsigned num_parts = 0;
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bool need_prolog = si_vs_needs_prolog(sel, &shader->key.part.vs.prolog);
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bool has_prolog = false;
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LLVMValueRef main_fn = ctx.main_fn;
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if (ngg_cull_main_fn) {
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if (need_prolog) {
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if (si_vs_needs_prolog(sel, &shader->key.part.vs.prolog,
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&shader->key, true)) {
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union si_shader_part_key prolog_key;
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si_get_vs_prolog_key(&sel->info,
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shader->info.num_input_sgprs,
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@ -2951,11 +2971,13 @@ int si_compile_shader(struct si_screen *sscreen,
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prolog_key.vs_prolog.is_monolithic = true;
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si_build_vs_prolog_function(&ctx, &prolog_key);
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parts[num_parts++] = ctx.main_fn;
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has_prolog = true;
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}
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parts[num_parts++] = ngg_cull_main_fn;
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}
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if (need_prolog) {
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if (si_vs_needs_prolog(sel, &shader->key.part.vs.prolog,
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&shader->key, false)) {
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union si_shader_part_key prolog_key;
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si_get_vs_prolog_key(&sel->info,
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shader->info.num_input_sgprs,
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@ -2965,11 +2987,12 @@ int si_compile_shader(struct si_screen *sscreen,
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prolog_key.vs_prolog.is_monolithic = true;
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si_build_vs_prolog_function(&ctx, &prolog_key);
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parts[num_parts++] = ctx.main_fn;
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has_prolog = true;
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}
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parts[num_parts++] = main_fn;
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si_build_wrapper_function(&ctx, parts, num_parts,
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need_prolog ? 1 : 0, 0);
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has_prolog ? 1 : 0, 0);
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if (ctx.shader->key.opt.vs_as_prim_discard_cs)
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si_build_prim_discard_compute_shader(&ctx);
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@ -2986,7 +3009,8 @@ int si_compile_shader(struct si_screen *sscreen,
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struct si_shader_selector *ls = shader->key.part.tcs.ls;
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LLVMValueRef parts[4];
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bool vs_needs_prolog =
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si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
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si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog,
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&shader->key, false);
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/* TCS main part */
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parts[2] = ctx.main_fn;
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@ -3086,7 +3110,8 @@ int si_compile_shader(struct si_screen *sscreen,
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/* ES prolog */
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if (es->type == PIPE_SHADER_VERTEX &&
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si_vs_needs_prolog(es, &shader->key.part.gs.vs_prolog)) {
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si_vs_needs_prolog(es, &shader->key.part.gs.vs_prolog,
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&shader->key, false)) {
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union si_shader_part_key vs_prolog_key;
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si_get_vs_prolog_key(&es->info,
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shader_es.info.num_input_sgprs,
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@ -3391,6 +3416,72 @@ static void si_build_vs_prolog_function(struct si_shader_context *ctx,
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}
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}
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if (key->vs_prolog.gs_fast_launch_tri_list ||
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key->vs_prolog.gs_fast_launch_tri_strip) {
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LLVMValueRef wave_id, thread_id_in_tg;
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wave_id = si_unpack_param(ctx, input_sgpr_param[3], 24, 4);
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thread_id_in_tg = ac_build_imad(&ctx->ac, wave_id,
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LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false),
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ac_get_thread_id(&ctx->ac));
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/* The GS fast launch initializes all VGPRs to the value of
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* the first thread, so we have to add the thread ID.
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*
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* Only these are initialized by the hw:
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* VGPR2: Base Primitive ID
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* VGPR5: Base Vertex ID
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* VGPR6: Instance ID
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*/
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/* Put the vertex thread IDs into VGPRs as-is instead of packing them.
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* The NGG cull shader will read them from there.
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*/
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if (key->vs_prolog.gs_fast_launch_tri_list) {
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input_vgprs[0] = ac_build_imad(&ctx->ac, thread_id_in_tg, /* gs_vtx01_offset */
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LLVMConstInt(ctx->i32, 3, 0), /* Vertex 0 */
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LLVMConstInt(ctx->i32, 0, 0));
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input_vgprs[1] = ac_build_imad(&ctx->ac, thread_id_in_tg, /* gs_vtx23_offset */
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LLVMConstInt(ctx->i32, 3, 0), /* Vertex 1 */
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LLVMConstInt(ctx->i32, 1, 0));
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input_vgprs[4] = ac_build_imad(&ctx->ac, thread_id_in_tg, /* gs_vtx45_offset */
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LLVMConstInt(ctx->i32, 3, 0), /* Vertex 2 */
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LLVMConstInt(ctx->i32, 2, 0));
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} else {
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assert(key->vs_prolog.gs_fast_launch_tri_strip);
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LLVMBuilderRef builder = ctx->ac.builder;
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/* Triangle indices: */
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LLVMValueRef index[3] = {
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thread_id_in_tg,
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LLVMBuildAdd(builder, thread_id_in_tg,
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LLVMConstInt(ctx->i32, 1, 0), ""),
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LLVMBuildAdd(builder, thread_id_in_tg,
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LLVMConstInt(ctx->i32, 2, 0), ""),
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};
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LLVMValueRef is_odd = LLVMBuildTrunc(ctx->ac.builder,
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thread_id_in_tg, ctx->i1, "");
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LLVMValueRef flatshade_first =
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LLVMBuildICmp(builder, LLVMIntEQ,
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si_unpack_param(ctx, ctx->vs_state_bits, 4, 2),
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ctx->i32_0, "");
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ac_build_triangle_strip_indices_to_triangle(&ctx->ac, is_odd,
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flatshade_first, index);
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input_vgprs[0] = index[0];
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input_vgprs[1] = index[1];
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input_vgprs[4] = index[2];
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}
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/* Triangles always have all edge flags set initially. */
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input_vgprs[3] = LLVMConstInt(ctx->i32, 0x7 << 8, 0);
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input_vgprs[2] = LLVMBuildAdd(ctx->ac.builder, input_vgprs[2],
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thread_id_in_tg, ""); /* PrimID */
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input_vgprs[5] = LLVMBuildAdd(ctx->ac.builder, input_vgprs[5],
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thread_id_in_tg, ""); /* VertexID */
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input_vgprs[8] = input_vgprs[6]; /* InstanceID */
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}
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unsigned vertex_id_vgpr = first_vs_vgpr;
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unsigned instance_id_vgpr =
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ctx->screen->info.chip_class >= GFX10 ?
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@ -3498,7 +3589,7 @@ static bool si_get_vs_prolog(struct si_screen *sscreen,
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{
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struct si_shader_selector *vs = main_part->selector;
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if (!si_vs_needs_prolog(vs, key))
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if (!si_vs_needs_prolog(vs, key, &shader->key, false))
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return true;
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/* Get the prolog. */
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@ -273,9 +273,12 @@ enum {
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SI_VS_BLIT_SGPRS_POS_TEXCOORD = 9,
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};
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#define SI_NGG_CULL_VIEW_SMALLPRIMS (1 << 0) /* view.xy + small prims */
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#define SI_NGG_CULL_BACK_FACE (1 << 1) /* back faces */
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#define SI_NGG_CULL_FRONT_FACE (1 << 2) /* front faces */
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#define SI_NGG_CULL_VIEW_SMALLPRIMS (1 << 0) /* view.xy + small prims */
|
||||
#define SI_NGG_CULL_BACK_FACE (1 << 1) /* back faces */
|
||||
#define SI_NGG_CULL_FRONT_FACE (1 << 2) /* front faces */
|
||||
#define SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST (1 << 3) /* GS fast launch: triangles */
|
||||
#define SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP (1 << 4) /* GS fast launch: triangle strip */
|
||||
#define SI_NGG_CULL_GS_FAST_LAUNCH_ALL (0x3 << 3) /* GS fast launch (both prim types) */
|
||||
|
||||
/**
|
||||
* For VS shader keys, describe any fixups required for vertex fetch.
|
||||
|
|
@ -564,6 +567,8 @@ union si_shader_part_key {
|
|||
unsigned as_es:1;
|
||||
unsigned as_ngg:1;
|
||||
unsigned has_ngg_cull_inputs:1; /* from the NGG cull shader */
|
||||
unsigned gs_fast_launch_tri_list:1; /* for NGG culling */
|
||||
unsigned gs_fast_launch_tri_strip:1; /* for NGG culling */
|
||||
/* Prologs for monolithic shaders shouldn't set EXEC. */
|
||||
unsigned is_monolithic:1;
|
||||
} vs_prolog;
|
||||
|
|
@ -655,7 +660,7 @@ struct si_shader_key {
|
|||
unsigned clip_disable:1;
|
||||
|
||||
/* For NGG VS and TES. */
|
||||
unsigned ngg_culling:3; /* SI_NGG_CULL_* */
|
||||
unsigned ngg_culling:5; /* SI_NGG_CULL_* */
|
||||
|
||||
/* For shaders where monolithic variants have better code.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -2042,12 +2042,11 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
|
|||
if (sctx->ngg &&
|
||||
rast_prim == PIPE_PRIM_TRIANGLES &&
|
||||
(sctx->screen->always_use_ngg_culling ||
|
||||
/* At least 1500 non-indexed triangles (4500 vertices) are needed
|
||||
* per draw call (no TES/GS) to enable NGG culling. Triangle strips
|
||||
* don't need this, because they have good reuse and therefore
|
||||
* perform the same as indexed triangles.
|
||||
/* At least 1024 non-indexed vertices (8 subgroups) are needed
|
||||
* per draw call (no TES/GS) to enable NGG culling.
|
||||
*/
|
||||
(!index_size && prim == PIPE_PRIM_TRIANGLES && direct_count > 4500 &&
|
||||
(!index_size && direct_count >= 1024 &&
|
||||
(prim == PIPE_PRIM_TRIANGLES || prim == PIPE_PRIM_TRIANGLE_STRIP) &&
|
||||
!sctx->tes_shader.cso && !sctx->gs_shader.cso)) &&
|
||||
si_get_vs(sctx)->cso->ngg_culling_allowed) {
|
||||
unsigned ngg_culling = 0;
|
||||
|
|
@ -2068,6 +2067,18 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
|
|||
if (sctx->viewports.y_inverted ? rs->cull_front : rs->cull_back)
|
||||
ngg_culling |= SI_NGG_CULL_BACK_FACE;
|
||||
}
|
||||
|
||||
/* Use NGG fast launch for certain non-indexed primitive types.
|
||||
* A draw must have at least 1 full primitive.
|
||||
*/
|
||||
if (ngg_culling && !index_size && direct_count >= 3 &&
|
||||
!sctx->tes_shader.cso && !sctx->gs_shader.cso) {
|
||||
if (prim == PIPE_PRIM_TRIANGLES)
|
||||
ngg_culling |= SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST;
|
||||
else if (prim == PIPE_PRIM_TRIANGLE_STRIP)
|
||||
ngg_culling |= SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP;
|
||||
}
|
||||
|
||||
if (ngg_culling != sctx->ngg_culling) {
|
||||
sctx->ngg_culling = ngg_culling;
|
||||
sctx->do_update_shaders = true;
|
||||
|
|
|
|||
|
|
@ -1234,6 +1234,8 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
|
|||
late_alloc_wave64 = 0;
|
||||
else if (num_cu_per_sh <= 6)
|
||||
late_alloc_wave64 = num_cu_per_sh - 2; /* All CUs enabled */
|
||||
else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
|
||||
late_alloc_wave64 = (num_cu_per_sh - 2) * 6;
|
||||
else
|
||||
late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
|
||||
|
||||
|
|
@ -1316,26 +1318,36 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
|
|||
shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
|
||||
S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
|
||||
|
||||
shader->ge_cntl =
|
||||
S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
|
||||
S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
|
||||
S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
|
||||
if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST) {
|
||||
shader->ge_cntl =
|
||||
S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
|
||||
S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims * 3);
|
||||
} else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP) {
|
||||
shader->ge_cntl =
|
||||
S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
|
||||
S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims + 2);
|
||||
} else {
|
||||
shader->ge_cntl =
|
||||
S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
|
||||
S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
|
||||
S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
|
||||
|
||||
/* Bug workaround for a possible hang with non-tessellation cases.
|
||||
* Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
|
||||
*
|
||||
* Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
|
||||
*/
|
||||
if ((sscreen->info.family == CHIP_NAVI10 ||
|
||||
sscreen->info.family == CHIP_NAVI12 ||
|
||||
sscreen->info.family == CHIP_NAVI14) &&
|
||||
(es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
|
||||
shader->ngg.hw_max_esverts != 256) {
|
||||
shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
|
||||
/* Bug workaround for a possible hang with non-tessellation cases.
|
||||
* Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
|
||||
*
|
||||
* Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
|
||||
*/
|
||||
if ((sscreen->info.family == CHIP_NAVI10 ||
|
||||
sscreen->info.family == CHIP_NAVI12 ||
|
||||
sscreen->info.family == CHIP_NAVI14) &&
|
||||
(es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
|
||||
shader->ngg.hw_max_esverts != 256) {
|
||||
shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
|
||||
|
||||
if (shader->ngg.hw_max_esverts > 5) {
|
||||
shader->ge_cntl |=
|
||||
S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
|
||||
if (shader->ngg.hw_max_esverts > 5) {
|
||||
shader->ge_cntl |=
|
||||
S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -3954,6 +3966,7 @@ static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
|
|||
|
||||
if (key.u.ngg) {
|
||||
stages |= S_028B54_PRIMGEN_EN(1) |
|
||||
S_028B54_GS_FAST_LAUNCH(key.u.ngg_gs_fast_launch) |
|
||||
S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
|
||||
S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
|
||||
} else if (key.u.gs)
|
||||
|
|
@ -4109,8 +4122,13 @@ bool si_update_shaders(struct si_context *sctx)
|
|||
}
|
||||
|
||||
/* This must be done after the shader variant is selected. */
|
||||
if (sctx->ngg)
|
||||
key.u.ngg_passthrough = gfx10_is_ngg_passthrough(si_get_vs(sctx)->current);
|
||||
if (sctx->ngg) {
|
||||
struct si_shader *vs = si_get_vs(sctx)->current;
|
||||
|
||||
key.u.ngg_passthrough = gfx10_is_ngg_passthrough(vs);
|
||||
key.u.ngg_gs_fast_launch = !!(vs->key.opt.ngg_culling &
|
||||
SI_NGG_CULL_GS_FAST_LAUNCH_ALL);
|
||||
}
|
||||
|
||||
si_update_vgt_shader_config(sctx, key);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue