mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-05 16:08:04 +02:00
etnaviv: add debug switch to disable texture descriptor usage
Halti5 GPUs still support the state based sampler configuration, alongside the new texture descriptor based method. Allow to switch between both methods with a debug switch, to allow easy comparisons between them. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32662>
This commit is contained in:
parent
66512cd897
commit
734ba8d785
4 changed files with 6 additions and 4 deletions
|
|
@ -494,7 +494,7 @@ etna_reset_gpu_state(struct etna_context *ctx)
|
|||
}
|
||||
if (screen->info->halti >= 5) { /* Only on HALTI5+ */
|
||||
etna_set_state(stream, VIVS_NTE_DESCRIPTOR_CONTROL,
|
||||
VIVS_NTE_DESCRIPTOR_CONTROL_ENABLE);
|
||||
COND(!DBG_ENABLED(ETNA_DBG_NO_TEXDESC), VIVS_NTE_DESCRIPTOR_CONTROL_ENABLE));
|
||||
etna_set_state(stream, VIVS_FE_HALTI5_UNK007D8, 0x00000002);
|
||||
etna_set_state(stream, VIVS_PS_SAMPLER_BASE, 0x00000000);
|
||||
etna_set_state(stream, VIVS_VS_SAMPLER_BASE, 0x00000020);
|
||||
|
|
@ -512,7 +512,7 @@ etna_reset_gpu_state(struct etna_context *ctx)
|
|||
etna_set_state(stream, VIVS_RS_SINGLE_BUFFER, COND(screen->specs.single_buffer, VIVS_RS_SINGLE_BUFFER_ENABLE));
|
||||
}
|
||||
|
||||
if (screen->info->halti >= 5) {
|
||||
if (screen->info->halti >= 5 && !DBG_ENABLED(ETNA_DBG_NO_TEXDESC)) {
|
||||
/* TXDESC cache flush - do this once at the beginning, as texture
|
||||
* descriptors are only written by the CPU once, then patched by the kernel
|
||||
* before command stream submission. It does not need flushing if the
|
||||
|
|
|
|||
|
|
@ -64,6 +64,7 @@ enum etna_dbg {
|
|||
ETNA_DBG_SHARED_TS = BITFIELD_BIT(27), /* Enable TS sharing */
|
||||
ETNA_DBG_NPU_PARALLEL = BITFIELD_BIT(28), /* Enable parallelism inside NPU batches (unsafe) */
|
||||
ETNA_DBG_NPU_NO_BATCHING = BITFIELD_BIT(29), /* Disable batching NPU jobs */
|
||||
ETNA_DBG_NO_TEXDESC = BITFIELD_BIT(30), /* Disable texture descriptor */
|
||||
};
|
||||
|
||||
extern int etna_mesa_debug; /* set in etnaviv_screen.c from ETNA_MESA_DEBUG */
|
||||
|
|
|
|||
|
|
@ -79,6 +79,7 @@ static const struct debug_named_value etna_debug_options[] = {
|
|||
{"perf", ETNA_DBG_PERF, "Enable performance warnings"},
|
||||
{"npu_parallel", ETNA_DBG_NPU_PARALLEL, "Enable parallelism inside NPU batches (unsafe)"},
|
||||
{"npu_no_batching",ETNA_DBG_NPU_NO_BATCHING, "Disable batching NPU jobs"},
|
||||
{"no_texdesc" ,ETNA_DBG_NO_TEXDESC, "Disable texture descriptor"},
|
||||
DEBUG_NAMED_VALUE_END
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -367,7 +367,7 @@ etna_texture_init(struct pipe_context *pctx)
|
|||
pctx->set_sampler_views = etna_set_sampler_views;
|
||||
pctx->texture_barrier = etna_texture_barrier;
|
||||
|
||||
if (screen->info->halti >= 5) {
|
||||
if (screen->info->halti >= 5 && !DBG_ENABLED(ETNA_DBG_NO_TEXDESC)) {
|
||||
u_suballocator_init(&ctx->tex_desc_allocator, pctx, 4096, 0,
|
||||
PIPE_USAGE_IMMUTABLE, 0, true);
|
||||
etna_texture_desc_init(pctx);
|
||||
|
|
@ -382,6 +382,6 @@ etna_texture_fini(struct pipe_context *pctx)
|
|||
struct etna_context *ctx = etna_context(pctx);
|
||||
struct etna_screen *screen = ctx->screen;
|
||||
|
||||
if (screen->info->halti >= 5)
|
||||
if (screen->info->halti >= 5 && !DBG_ENABLED(ETNA_DBG_NO_TEXDESC))
|
||||
u_suballocator_destroy(&ctx->tex_desc_allocator);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue