diff --git a/.pick_status.json b/.pick_status.json
index cbc9b8bca90..c5e1a5447f6 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -34,7 +34,7 @@
         "description": "anv: implement undocumented tile cache flush requirements",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null,
         "notes": null
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index bc5a14a4c14..c3796cfdaa5 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -4998,6 +4998,16 @@ anv_image_has_private_binding(const struct anv_image *image)
    return private_binding.memory_range.size != 0;
 }
 
+static inline bool
+anv_image_format_is_d16_or_s8(const struct anv_image *image)
+{
+   return image->vk.format == VK_FORMAT_D16_UNORM ||
+      image->vk.format == VK_FORMAT_D16_UNORM_S8_UINT ||
+      image->vk.format == VK_FORMAT_D24_UNORM_S8_UINT ||
+      image->vk.format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
+      image->vk.format == VK_FORMAT_S8_UINT;
+}
+
 /* The ordering of this enum is important */
 enum anv_fast_clear_type {
    /** Image does not have/support any fast-clear blocks */
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index e2e3100668b..e3ffe76a166 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -394,6 +394,23 @@ transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
       anv_image_hiz_op(cmd_buffer, image, VK_IMAGE_ASPECT_DEPTH_BIT,
                        0, base_layer, layer_count, ISL_AUX_OP_AMBIGUATE);
    }
+
+#if GFX_VER == 12
+   /* Depth/Stencil writes by the render pipeline to D16 & S8 formats use a
+    * different pairing bit for the compression cache line. This means that
+    * there is potential for aliasing with the wrong cache if you use another
+    * format OR a piece of HW that does not use the same pairing. To avoid
+    * this, flush the tile cache as the compression data does not live in the
+    * color/depth cache.
+    */
+   if (image->planes[depth_plane].aux_usage == ISL_AUX_USAGE_HIZ_CCS &&
+       final_needs_depth && !initial_depth_valid &&
+       anv_image_format_is_d16_or_s8(image)) {
+      anv_add_pending_pipe_bits(cmd_buffer,
+                                ANV_PIPE_TILE_CACHE_FLUSH_BIT,
+                                "D16 or S8 HIZ-CCS flush");
+   }
+#endif
 }
 
 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
@@ -449,6 +466,19 @@ transition_stencil_buffer(struct anv_cmd_buffer *cmd_buffer,
                              clear_rect, 0 /* Stencil clear value */);
       }
    }
+
+   /* Depth/Stencil writes by the render pipeline to D16 & S8 formats use a
+    * different pairing bit for the compression cache line. This means that
+    * there is potential for aliasing with the wrong cache if you use another
+    * format OR a piece of HW that does not use the same pairing. To avoid
+    * this, flush the tile cache as the compression data does not live in the
+    * color/depth cache.
+    */
+   if (anv_image_format_is_d16_or_s8(image)) {
+      anv_add_pending_pipe_bits(cmd_buffer,
+                                ANV_PIPE_TILE_CACHE_FLUSH_BIT,
+                                "D16 or S8 HIZ-CCS flush");
+   }
 #endif
 }